UT8SF2M40MCPC datasheet(6/23 Pages) AEROFLEX

6 / 23 page

36-00-01-00

Ver. 1.0.0

Aeroflex Microelectronics Solutions - HiRel

READY Status

The UT8SF2M40 device operates as a Synchronous SRAM

device. Data integrity housekeeping activities are performed in

the background during normal user activity. These

housekeeping activities are performed on a regular basis.

However, when a housekeeping activity sequence cannot be

completed due to user conflict for memory space, the READY

pin asserts signifying to the user that an idle cycle is required.

Please reference applications note AN-MEM-004 for more

information.

Byte Write Enables BWE[4:0]

The UT8SF2M40 device employs six byte write enable inputs

to be used in conjunction with WE to qualify each associated

byte of data into the memory. When WE is HIGH, the device

is in read mode where all BWE[4:0] are don’t cares. When

WE is LOW, each BWE[4:0] must also be low to write the

associated data input pins into memory. Data input pins whose

associated byte write enable pin is HIGH, will be masked.

Sleep Mode

The ZZ input lead is a synchronous input. Asserting the ZZ pin

HIGH places the SSRAM into a power conservative "sleep"

mode. To assure the completion of previous commands and

through the pipeline prior to entering sleep mode, a minimum

of two full clock cycles (tZZS) are required between the last

operation command and asserting the ZZ input. While in sleep

mode, data integrity is guaranteed. Changing the input clock

frequency or halting the input clock may be executed during

sleep mode. The device must be deselected prior to entering

sleep mode and remain deselected for the duration of tZZREC

after the ZZ input returns LOW.

Shutdown Mode

The SHUTDOWN input pin is an asynchronous input.

Asserting SHUTDOWN places the device in a power saving

shutdown mode. The system clock can be stopped. Memory

contents are not maintained in shutdown mode. The SSRAM

requires a reset cycle upon exiting shutdown mode.

Power Up/ Down Requirements

The SSRAM requires that VDD < VDDQ at all times. The

SSRAM does require the user to provide an external reset after

initial power application, exiting shutdown mode, or any

power interruption to the device input voltage outside the

specified limit. Performing a reset requires the assertion of the

RESET device input lead (LOW) for a minimum of 1us

(tRLRH). After the RESET input is returned HIGH, the device

requires 50us (tSHTDWNREC) to complete the reset operation.

Once the reset operation is complete, the device requires an

additional 20us (tCR) to synchronize the clock input, providing

a stable input clock is present. The device READY output lead

asserts HIGH once tCR is satisfied at the next rising clock. The

READY out lead HIGH indicates the device is available for

normal operations. For power down it is required that VDD and

VDDQ be powered down to <0.5V for a minimum of 100ms.

Clock Conditioning Requirements

The CLK signal input requirements are given in the Clock

section of the AC Characterizations. AC Characterization

performances listed herein are based on providing a clock

input signal meeting these requirements.

Table 2. Byte Write Enable to Data Input Pins

Byte Write

Enable Input

Data Input Pins

BWE0

DQ[7:0]

BWE1

DQ[15:8]

BWE2

DQ[23:16]

BWE3

DQ[31:24]

BWE4

DQ[39:32]

Table 3. Linear Burst Address Table

(MODE=VSS)

Starting

Address

Second

Address

Third

Address

Fourth

Address

A1, A0

Table 4. Interleaved Burst Address Table

(MODE=VDDQ)

Starting

Address

Second

Address

Third

Address

Fourth

Address

A1, A0

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