ADC16071CIWM datasheet(13/20 Pages) NSC

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Pin Description (Continued)

FSO

This is the Frame Sync Output pin FSO is used

synchronize

external

device

the

ADC16071ADC16471’s 32 SCO cycle data

transmission frame The format of the signal on

FSO

depends on the logic level applied to the

SFMT

pin See the Serial Interface section for

details

TSI

This is the Time Slot Input pin TSI can be used

to allow two ADC16071ADC16471’s to share a

single serial data line The logic level applied to

TSI

controls the active state of the ADC16071

ADC16471’s DOE pin See the Serial Interface

and the Two Channel Multiplexed Operation

sections for details

DOE

This is the Data Output Enable pin DOE is used

to control SDO’s TRI-STATE output buffer The

active state of DOE is controlled by the logic lev-

el applied to the TSI pin See the Serial Inter-

face

and the Two Channel Multiplexed Opera-

tion

sections for details

Applications Information

TYPICAL PERFORMANCE RESULTS

Figure 6 shows a 16k point FFT plot of the baseband output

spectrum during conversion of a 24 kHz input signal

CLOCK GENERATION

The ADC16071ADC16471 requires a sampling-clock sig-

nal that is free of ringing (overundershoot of no more than

100 mVp-p) and has a rise and fall time in the range of 3 ns–

10 ns We have tested and recommended crystal clock os-

cillators from Ecliptek (EC1100 series) and SaRonix

(NCH060 and NCH080 series) Both of these families use

HCMOS logic circuitry for very fast rise and fall times

TLH11454 – 13

FIGURE 6 Typical Performance of the ADC16071ADC16471 at fS e 192 kHz fIN e 24 kHz

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