ADV3225ACPZ datasheet(21/24 Pages) AD

21 / 24 page

Data Sheet

ADV3224/ADV3225

Rev. B | Page 21 of 24

THEORY OF OPERATION

The ADV3224 (G = +1) and ADV3225 (G = +2) are crosspoint

arrays with eight outputs, each of which can be connected to

any one of 16 inputs. Organized by output row, 16 switchable

input transconductance stages are connected to each output

buffer to form 16-to-1 multiplexers. There are eight of these

multiplexers, each with its inputs wired in parallel, for a total array

of 128 transconductance stages forming a multicast-capable

crosspoint switch. Each input is buffered and is not loaded by

the outputs, simplifying the construction of larger arrays using the

ADV3224 or ADV3225 as a building block.

Decoding logic for each output selects one (or none) of the

transconductance stages to drive the output stage. The enabled

transconductance stage drives the output stage, and feedback

forms a closed-loop amplifier. A mask programmable feedback

network sets the closed-loop signal gain. For the ADV3224, this

gain is +1, and for the ADV3225, this gain is +2.

The output stage of the ADV3224 or ADV3225 is designed for

low differential gain and phase error when driving composite

video signals. It also provides slew current for a fast pulse response

when driving component video signals. Unlike many multiplexer

designs, these requirements are balanced such that large signal

bandwidth is very similar to small signal bandwidth. The design

load is 150 Ω, but provisions are made to drive loads as low as

100 Ω when on-chip power dissipation limits are not exceeded.

The outputs of the ADV3224/ADV3225 can be disabled to mini-

mize on-chip power dissipation. When disabled, there is no

feedback network loading the output. This high disabled output

impedance allows multiple ICs to be bussed together without

additional buffering. Take care to reduce output capacitance,

which results in more overshoot and frequency domain

peaking.

A series of internal amplifiers drives internal nodes such that a

wideband high impedance is presented at the disabled output,

even while the output bus is under large signal swings. To keep

these internal amplifiers in their linear range of operation when

the outputs are disabled and driven externally, do not allow the

voltage applied to them to exceed the valid output swing range

for the ADV3224/ADV3225. If the disabled outputs are left

floating, they may exhibit high enable glitches. If necessary,

the disabled output can be kept from drifting out of range by

applying an output load resistor to ground.

The connection of the ADV3224/ADV3225 is controlled by a

flexible TTL-compatible logic interface. Either parallel or serial

loading into a first rank of latches preprograms each output. A

global update signal moves the programming data into the second

rank of latches, simultaneously updating all outputs. In serial

mode, a serial output pin allows devices to be daisy-chained

together for single pin programming of multiple ICs. A power-

on reset pin is available to avoid bus conflicts by disabling all

outputs. This power-on reset clears the second rank of latches

but does not clear the first rank of latches. In serial mode, pre-

programming individual inputs is not possible and the entire

shift register must be flushed.

To easily interface to ground referenced video signals, the

ADV3224/ADV3225 operate on split ±5 V supplies. The logic

inputs and output run on a single 5 V supply, and the logic

inputs switch at approximately 1.6 V for compatibility with a

variety of logic families. The serial output buffer is a rail-to-

rail output stage with 5 mA of drive capability.

ADV3225ACPZ Datasheet(PDF) 21 Page - Analog Devices

ADV3225ACPZ Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL