ADN2913 datasheet(13/37 Pages) AD

Part #	ADN2913

Description	Continuous Rate 6.5 Mbps to 8.5 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ

PDF	37 Pages

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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13 / 37 page

Data Sheet

ADN2913

Rev. A | Page 13 of 37

I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTIONS

SLAVE ADDRESS[6:0]

SET BY

PIN 22

MSB = 1

0 = W

1 = R

R/W

CTRL.

Figure 18. Slave Address Configuration

SLAVE ADDR, LSB = 0 (W)

A(S)

DATA

SUBADDR

A(S)

DATA

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

Figure 19. I2C Write Data Transfer

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A(M) = NO ACKNOWLEDGE BY MASTER

SLAVE ADDR, LSB = 0 (W)

SLAVE ADDR, LSB = 1 (R)

A(S)

SUBADDR

A(S) DATA A(M)

DATA

A(M)

Figure 20. I2C Read Data Transfer

START BIT

STOP BIT

ACK

SLAVE ADDR[4:0]

SLAVE ADDRESS

SUBADDRESS

DATA

SUBADDR[6:1]

DATA[6:1]

SCK

SDA

Figure 21. I2C Data Transfer Timing

tBUF

SDA

SCK

tLOW

tHD;STA

tHD;DAT

tSU;DAT

tHIGH

tSU;STA

tSU;STO

tHD;STA

Figure 22. I2C Interface Timing Diagram

ADN2913 Datasheet(PDF) 13 Page - Analog Devices

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