CLC021 datasheet(10/18 Pages) NSC

10 / 18 page

Device Operation (Continued)

BUILT-IN SELF-TEST (BIST)

The CLC021 has a built-in self-test (BIST) function. The

BIST performs a comprehensive go/no-go test of the device.

The test uses either a full-field colour bar for NTSC or a PLL

pathological for PAL as the test data pattern. Data is input

internally in the input data register, processed through the

device and tested for errors. A go/no-go indication is given at

the Test_Output. Table 1 gives device pin functions and

Table 2 gives the test pattern codes used for this function.

The signal level at Test_Output, pin 3, indicates a pass or fail

condition.

The BIST is initiated by applying the code for the desired

BIST to D0 through D3 (D9 through D4 are 00h) and a 27

MHz clock at the P

CLK input. Since all parallel data inputs are

equipped with an internal pull-down device, only those inputs

D0 through D3 which require a logic-1 need be pulled high.

After the Lock_Detect output goes high indicating the VCO is

locked on frequency, TPG_Enable, pin 29, is taken to a logic

high. The Lock_Detect output may be temporarily connected

to TPG_Enable to automate BIST operation. Test_Output,

pin 3, is monitored for a pass/fail indication. If no errors have

been detected, this output will go to a logic high level ap-

proximately 2 field intervals after TPG_Enable is taken high.

If errors have been detected in the internal circuitry of the

CLC021, Test_Output will remain low until the test is termi-

nated. The BIST is terminated by taking TPG _Enable to a

logic low. Continuous serial data output is available during

the test.

10136815

FIGURE 4. Power-On Reset Sequence

10136814

FIGURE 5. Power-On Reset Sequence with Manual Reset

CLC021 Datasheet(PDF) 10 Page - National Semiconductor (TI)