CLC021 datasheet(11/18 Pages) NSC

11 / 18 page

Device Operation (Continued)

TEST PATTERN GENERATOR

The CLC021 includes an on-board test pattern generator

(TPG). Four full-field component video test patterns for both

NTSC and PAL standards, and 4x3 and 16x9 raster sizes are

produced. The test patterns are: flat-field black, PLL patho-

logical, equalizer (EQ) pathological and a modified 75%,

8-colour vertical bar pattern. The pathologicals follow recom-

mendations contained in SMPTE RP 178–1996 regarding

the test data used. The colour bar pattern does not incorpo-

rate bandwidth limiting coding in the chroma and luma data

when transitioning between the bars. For this reason, it may

not be suitable for use as a visual test pattern or for input to

video D-to-A conversion devices unless measures are taken

to restrict the production of out-of-band frequency compo-

nents.

The TPG is operated by applying the code for the desired

test pattern to D0 through D3 (D4 through D9 are 00h). Since

all parallel data inputs are equipped with internal pull-down

devices, only those inputs D0 through D3 which require a

logic-1 need be pulled high. Next, apply a 27 MHz or 36 MHz

signal, appropriate to the raster size desired, at the P

CLK

input and wait until the Lock_Detect output goes true indi-

cating the VCO is locked on frequency. Then, take

TPG_Enable, pin 29, to a logic high. The serial test pattern

data appears on the SDO outputs. The Lock_Detect output

may be temporarily connected to TPG_Enable to automate

TPG operation. The TPG mode is exited by taking TPG_En-

able to a logic low. Table 1 gives device pin functions for this

mode. Table 2 gives the available test patterns and selection

codes.

10136806

FIGURE 6. Built-In Self-Test Control Sequence

10136807

FIGURE 7. Test Pattern Generator Control Sequence

CLC021 Datasheet(PDF) 11 Page - National Semiconductor (TI)