CY7C68013
Document #: 38-08012 Rev. *E
Page 21 of 48
69
54
36
29
CTL0 or
FLAGA
Output
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status flag signal.
Defaults to programmable for the FIFO selected by the
FIFOADR[1:0] pins.
70
55
37
30
CTL1 or
FLAGB
Output
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
71
56
38
31
CTL2 or
FLAGC
Output
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0]
pins.
66
51
CTL3
Output
H
CTL3 is a GPIF control output.
67
52
CTL4
Output
H
CTL4 is a GPIF control output.
98
76
CTL5
Output
H
CTL5 is a GPIF control output.
32
26
20
13
IFCLK
I/O/Z
Z
Interface Clock, used for synchronously clocking data into or out
of the slave FIFOs. IFCLK also serves as a timing reference for all
slave FIFO control signals and GPIF. When internal clocking,
IFCONFIG.7 = 1, is used the IFCLK pin can be configured to
output 30/48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK
may be inverted, whether internally or externally sourced, by
setting the bit
IFCONFIG.4 =1.
28
22
INT4
Input
N/A
INT4 is the 8051 INT4 interrupt request input signal. The INT4 pin
is edge-sensitive, active HIGH.
106
84
INT5#
Input
N/A
INT5# is the 8051 INT5 interrupt request input signal. The INT5
pin is edge-sensitive, active LOW.
31
25
T2
Input
N/A
T2 is the active-HIGH T2 input signal to 8051 Timer2, which
provides the input to Timer2 when C/T2 = 1. When C/T2 = 0,
Timer2 does not use this pin.
30
24
T1
Input
N/A
T1 is the active-HIGH T1 signal for 8051 Timer1, which provides
the input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does
not use this bit.
29
23
T0
Input
N/A
T0 is the active-HIGH T0 signal for 8051 Timer0, which provides
the input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does
not use this bit.
53
43
RXD1
Input
N/A
RXD1is an active-HIGH input signal for 8051 UART1, which
provides data to the UART in all modes.
52
42
TXD1
Output
H
TXD1is an active-HIGH output pin from 8051 UART1, which
provides the output clock in sync mode, and the output data in
async mode.
51
41
RXD0
Input
N/A
RXD0 is the active-HIGH RXD0 input to 8051 UART0, which
provides data to the UART in all modes.
50
40
TXD0
Output
H
TXD0 is the active-HIGH TXD0 output from 8051 UART0, which
provides the output clock in sync mode, and the output data in
async mode.
42
CS#
Output
H
CS# is the active-LOW chip select for external memory.
41
32
WR#
Output
H
WR# is the active-LOW write strobe output for external memory.
Table 4-1. FX2 Pin Descriptions (continued)[5]
128
TQFP
100
TQFP
56
SSOP
56
QFN
Name
Type
Default
Description
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