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CY7C68013
Document #: 38-08012 Rev. *E
Page 31 of 48
9.3
Data Memory Read
data in
tCL
A[15..0]
tAV
tAV
RD#
tSTBL
tSTBH
tDH
D[7..0]
data in
tACC1
[12]
tDSU
Stretch = 0
Stretch = 1
tCL
A[15..0]
tAV
RD#
tDH
D[7..0]
tACC1
[12]
tDSU
CS#
CS#
tSCSL
OE#
tSOEL
Figure 9-2. Data Memory Read Timing Diagram
CLKOUT[10]
CLKOUT[10]
Parameter
Description
Min.
Typ.
Max.
Unit
Notes
tCL
1/CLKOUT Frequency
20.83
ns
48 MHz
41.66
ns
24 MHz
83.2
ns
12 MHz
tAV
Delay from Clock to Valid Address
10.7
ns
tSTBL
Clock to RD LOW
11
ns
tSTBH
Clock to RD HIGH
11
ns
tSCSL
Clock to CS LOW
13
ns
tSOEL
Clock to OE LOW
11.1
ns
tDSU
Data Set-up to Clock
9.6
ns
tDH
Data Hold Time
0
ns
Note:
12. tACC2 and tACC3 are computed from the above parameters as follows:
tACC2(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC2(48 MHz) = 3*tCL – tAV – tDSU = 43 ns
tACC3(24 MHz) = 5*tCL – tAV –tDSU = 190 ns
tACC3(48 MHz) = 5*tCL – tAV – tDSU = 86 ns.
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