AMC7812BSPAPR datasheet(76/92 Pages) TI1

76 / 92 page

AMC7812B

SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013

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HW-DAC-CLR-EN 1 Register (Read or Write, Address = 57h, Default = 0000h)

This register determines which DAC is in a clear state when the DAC-CLR-1 pin goes low.

MSB

LSB

BIT

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

H1CLR

Bits[14:3]

H1CLRn

Hardware clear DAC-n enable 1 bit.

0 = Pulling the DAC-CLR-1 pin low does not effect the state of DAC-n

1 = DAC-n is forced into a clear state when the DAC-CLR-1 pin goes low

DAC Configuration Register (Read or Write, Address = 58h, Default = 0000h)

MSB

LSB

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SLDA

Bits[11:0]

SLDA-n

DAC synchronous load enable bit.

0 = Asynchronous load is enabled. A write command to the DAC-n-data register immediately updates the DAC-n latch

and the output of DAC-n. The synchronous load DAC signal (ILDAC) does not affect DACn. the default value of SLDA-n

is '0'. The device updates the DAC latch only if the ILDAC bit is set ('1'), thereby eliminating unnecessary glitches. Any

DAC channels that are not accessed are not reloaded. When the DAC latch is updated, the corresponding output

changes to the new level immediately. Note that the SLDA-n bit is ignored in auto mode (DAC-n mode bits do not equal

'00'). In auto mode, the DAC latch is always updated asynchronously.

1 = Synchronous load is enabled. When internal load DAC signal ILDAC occurs, the DAC-n latch is loaded with the value

of the corresponding DACn-data register, and the output of DAC-n is updated immediately. The internal load DAC signal

ILDAC is generated by writing a '1' to the ILDAC bit in the AMC configuration register. In synchronous load, a write

command to the DAC-n-data register updates that register only, and does not change the DAC-n output.

NOTE

The DACs can be forced to a clear state immediately by the external DAC-CLR-n signal,

by alarm events, and by writing to the SW-DAC-CLR register. In these cases, the SLDA-n

bit is ignored.

DAC Gain Register (Read or Write, Address = 59h, Default = 0000h)

The DACn GAIN bits specify the output range of DACn.

MSB

LSB

BIT 15 BIT 14 BIT 13 BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DAC11

DAC10

DAC9

DAC8

DAC7

DAC6

DAC5

DAC4

DAC3

DAC2

DAC1

DAC0

GAIN

Bits[11:0]

DACnGAIN: DACn gain bits.

1 = Gain is 5 and the output is 0 V to 5 × VREF

0 = Gain is 2 and the output is 0 V to 2 × VREF

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