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DS90C124IVS/NOPB Datasheet(PDF) 14 Page - Texas Instruments |
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DS90C124IVS/NOPB Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 31 page  48 DIN[19] 47 DIN[18] 46 DIN[17] 45 DIN[16] 44 DIN[15] 43 VSSIT 42 VDDIT 41 DIN[14] 40 DIN[13] 39 DIN[12] 38 DIN[11] 37 DIN[10] 13 14 15 16 17 18 19 20 21 22 23 24 RESRVD VDDPT1 VSSPT1 VDDPT0 VSSPT0 DEN DOUT- DOUT+ VSSDR VDDDR PRE VSS DS90C241 48 PIN TQFP DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com DS90C241 Pin Diagram Serializer - DS90C241 Figure 17. TOP VIEW DS90C124 Deserializer Pin Descriptions Pin # Pin Name I/O Description LVCMOS PARALLEL INTERFACE PINS 25-28, ROUT[7:0] LVCMOS_O Receiver LVCMOS level Outputs – Group 1 31-34 13-16, ROUT[15:8] LVCMOS_O Receiver LVCMOS level Outputs – Group 2 21-24 3-6, 9- ROUT[23:16] LVCMOS_O Receiver LVCMOS level Outputs – Group 3 12 18 RCLK LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin. CONTROL AND CONFIGURATION PINS 43 RRFB LVCMOS_I Receiver Clock Edge Select Pin RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge. RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge. 48 REN LVCMOS_I Receiver Data Enable REN = H; ROUT[23-0] and RCLK are Enabled (ON). REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs are in TRI-STATE, PLL still operational and locked to TCLK. 1 RPWDNB LVCMOS_I Receiver Power Down Bar RPWDNB = H; Receiver is Enabled and ON RPWDNB = L; Receiver is in power down mode (Sleep), ROUT[23-0], RCLK, and LOCK are in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption. 17 LOCK LVCMOS_O LOCK indicates the status of the receiver PLL LOCK = H; receiver PLL is locked LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED 14 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 |
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