DP8572AM datasheet(14/22 Pages) NSC

14 / 22 page

Functional Description (Continued)

the chip is unlocked but only after another 30 ms min

63 ms max debounce time The system designer must en-

sure that his system is stable when power has returned

The power fail circuitry contains active linear circuitry that

draws supply current from VCC In some cases this may be

undesirable so this circuit can be disabled by masking the

power fail interrupt The power fail input can perform all

lock-out functions previously mentioned except that no ex-

ternal interrupt will be issued Note that the linear power fail

circuitry is switched off automatically when using VBB in

standby mode

LOW BATTERY INITIAL POWER ON DETECT AND

POWER FAIL TIME SAVE

There are three other functions provided on the DP8572A to

ease power supply control These are an initial Power On

detect circuit which also can be used as a time keeping

failure detect a low battery detect circuit and a time save

on power failure

On initial power up the Oscillator Fail Flag will be set to a

one and the real time clock start bit reset to a zero This

indicates that an oscillator fail event has occurred and time

keeping has failed

The Oscillator Fail flag will not be reset until the real-time

clock is started This allows the system to discriminate be-

tween an initial power-up and recovery from a power failure

If the battery backed mode is selected then bit D6 of the

Periodic Flag Register must be written low This will not af-

fect the contents of the Oscillator Fail Flag

Another status bit is the low battery detect This bit is set

only when the clock is operating under the VCC pin and

when the battery voltage is determined to be less than 21V

(typical) When the power fail interrupt enable bit is low it

disables the power fail circuit and will also shut off the low

battery voltage detection circuit as well

To relieve CPU overhead for saving time upon power failure

the Time Save Enable bit is provided to do this automatical-

ly (See also Reading the Clock Latched Read) The Time

Save Enable bit when set causes the Time Save RAM to

follow the contents of the clock This bit can be reset by

software but if set before a power failure occurs it will auto-

matically be reset when the clock switches to the battery

supply (not when a power failure is detected by the PFAIL

pin) Thus writing a one to the Time Save bit enables both a

software write or power fail write

SINGLE POWER SUPPLY APPLICATIONS

The DP8572A can be used in a single power supply applica-

tion To achieve this the VBB pin must be connected to

ground and the power connected to VCC and PFAIL pins

The Oscillator FailedSingle Supply bit in the Periodic Flag

oscillator battery reference circuit The power fail interrupt

should also be disabled This will turn off the linear power

fail detection circuits and will eliminate any quiescent power

drawn through these circuits Until the crystal select bits are

initialized the DP8572A may consume about 50 mA due to

arbitrary oscillator selection at power on

(This extra 50 mA is not consumed if the battery backed

mode is selected)

DETAILED REGISTER DESCRIPTION

There are 5 external address bits Thus the host microproc-

essor has access to 28 locations at one time An internal

switching scheme provides a total of 61 locations

This complete address space is organized into two pages

Page 0 contains two blocks of control registers timers real

time clock counters and special purpose RAM while page

1 contains general purpose RAM Using two blocks enables

the 9 control registers to be mapped into 5 locations The

only register that does not get switched is the Main Status

select bit as well as status information

A memory map is shown in

Figure 2 and register addressing

in Table III They show the name address and page loca-

tions for the DP8572A

TABLE III RegisterCounterRAM

Addressing for DP8572A

A0-4

Description

(Note 1) (Note 2)

CONTROL REGISTERS

Main Status Register

Periodic Flag Register

Time Save Control Register

Real Time Mode Register

Output Mode Register

Interrupt Control Register 0

Interrupt Control Register 1

COUNTERS (CLOCK CALENDAR)

1100 110 Seconds (0 – 99)

Seconds

(0 – 59)

Minutes

(0 – 59)

Hours

(1 – 12 0 – 23)

Days of

Month

(1 – 28293031)

Months

(1 – 12)

Years

(0 – 99)

Julian Date (LSB)

(0 – 99) (Note 3)

Julian Date

(0 – 3)

Day of Week

(1 – 7)

TIME COMPARE RAM

Sec Compare RAM

(0 – 59)

Min Compare RAM

(0 – 59)

Hours Compare

RAM

(1 – 12 0 – 23)

DOM Compare

RAM

(1 – 28293031)

Months Compare

RAM

(1 – 12)

DOW Compare RAM (1 – 7)

TIME SAVE RAM

Seconds Time Save RAM

Minutes Time Save RAM

Hours Time Save RAM

Day of Month Time Save RAM

Months Time Save RAM

RAM

RAMTest Mode Register

01 – 1F

2nd Page General Purpose RAM

Note 1

PSPage Select (Bit D7 of Main Status Register)

Note 2

RSRegister Select (Bit D6 of Main Status Register)

Note 3

The LSB counters count 0

x99 until the hundreds of days counter

reaches 3 Then the LSB counters count to 65 or 66 (if a leap year) The

rollover is from 365366 to 1

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