DP8572AM datasheet(17/22 Pages) NSC

17 / 22 page

Functional Description (Continued)

This bit is used to program the signal appearing at the

MFO output as follows

MFO Output Signal

Power Fail Interrupt

Buffered Crystal Oscillator

INTERRUPT CONTROL REGISTER 0

TLF9980 – 17

D0 – D5

These bits are used to enable one of the selected

periodic interrupts by writing a one into the appropriate bit

These interrupts are issued at the rollover of the clock For

example the minutes interrupt will be issued whenever the

minutes counter increments In all likelihood the interrupt

will be enabled asynchronously with the real time change

Therefore the very first interrupt will occur in less than the

periodic time chosen but after the first interrupt all subse-

quent interrupts will be spaced correctly These interrupts

are useful when minute second real time reading or task

switching is required When all six bits are written to a 0 this

disables periodic interrupts from the Main Status Register

and the interrupt pin If a battery backed mode is selected

and the DP8572A is in standby (VBB l VCC) then these bits

are controlled by D4 of the Real Time Mode Register

D6 and D7

General Purpose RAM

INTERRUPT CONTROL REGISTER 1

TLF9980 – 18

D0 – D5

Each of these bits are enable bits which will enable

a comparison between an individual clock counter and its

associated compare RAM If any bit is a zero then that

clock-RAM comparator is set to the ‘‘always equal’’ state

and the associated TIME COMPARE RAM byte can be used

as general purpose RAM However to ensure that an alarm

interrupt is not generated at bit D3 of the Main Status Regis-

ter all bits must be written to a logic zero

In order to generate an external alarm compare inter-

rupt to the mP from bit D3 of the Main Status Register this

bit must be written to a logic 1 If a battery backed mode is

selected and the DP8572A is in standby (VBB l VCC) then

this bit is controlled by D4 of the Real Time Mode Register

The MSB of this register is the enable bit for the Power

Fail Interrupt When this bit is set to a one an interrupt will

be generated to the mP when VBB l VCC If a battery

backed mode is selected and the DP8572A is in standby

(VBB l VCC) then this bit is controlled by D4 of the Real

Time Mode Register

This bit also enables the low battery detection analog cir-

cuitry

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