LMH0031

SNLS218A – JANUARY 2006 – REVISED APRIL 2013

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The Lock Detect is a logic-1 when the loop is locked and the CDR has acquired a phase of the incoming serial

data. This bit may be programmed as an output on the multi-function I/O bus. This bit is mapped to I/O port bit 4

in the default condition.

The VPG Filter Enable bit when set enables operation of the Video Pattern Generator filter. Operation of this

filter causes the insertion of transition codes in the chroma and luma data of colour bar test patterns where these

patterns change from one bar to the next. This filter reduces the magnitude of out-of-band frequency products

which are produced by abrupt transitions in the chroma and luma data when fed to D-to-A converters and picture

monitors.

The LMH0031 incorporates circuitry that implements a method for handling data that has been subjected to LSB

dithering. Data from the de-scrambler is routed for de-dithering. Control of this circuitry is via the De-Dither

Enable bit in the VIDEO INFO 0 control register. Recovery of data that has been dithered during the vertical

blanking interval can be selectively enabled by use of the V De-Dither Enable bit in the VIDEO INFO 0 control

register. The initial condition of De-Dither Enable and V De-Dither Enable is OFF.

VIDEO CONTROL 0 (register address 55h)

frequency detection and control voltage output for the VCXO. An external loop filter and voltage amplifier are

required to interface the control voltage output to the VCXO frequency control input. When this function is used,

function and required external support circuitry is explained in the Application Information section.

The SYNC DETECT ENABLE bit, when set, enables detection of TRS characters. This bit is normally set (ON).

The LSB CLIP ENABLE bit, when set, causes the two LSBs of TRS characters to be set to 00b as described in

ITU-R BT.601. This function is normally set (ON).

The NRZI ENABLE bit, when set, enables data to be converted from NRZI to NRZ. This bit is normally set (ON).

The DE-SCRAMBLE ENABLE bit, when set, enables de-scrambling of the incoming data according to

requirements of SMPTE 259M or SMPTE 292M. This bit is normally set (ON).

CAUTION

The default state of this register is 36h. If any of the normal operating features of the

descrambler are turned off, this register’s default data must be restored to resume

normal device operation.

REFERENCE CLOCK REGISTER (Address 67h)

The Reference Clock register controls operation of the CDR reference clock source. The CLKEN bit when reset

to a logic-0 enables the oscillator signal to be used by the LMH0031 as a reference. The default state of this bit

at power-on is enabled. In general, this function and bit should not be disabled. The INT_OSC EN bit enables the

internal crystal oscillator amplifier. By default this bit is a logic-0 and is therefore inactive at power-on. The device

expects an external 27MHz reference reference clock source to be connected to the XTALi/Ext Clk pin and

activated at power-on.

I/O PIN 0 THROUGH 7 CONFIGURATION REGISTERS (Addresses 0Fh through 16h)

The I/O Pin Configuration Registers are used to map individual bits of the multi-function I/O port to selected

bits of the Configuration and Control Registers. Table 6 gives the pin select codes for the Configuration and

Control register functions that may be mapped to the port. Pin[n] Select [5] controls whether the port pin is input

or output. The port pin will be an input when this bit is set and an output when reset. Input-only functions may not

be configured as outputs and vice versa. The remaining five Pin[n] Select [4:0] bits identify the particular Control

Register bit to be mapped.

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