LMH0031

SNLS218A – JANUARY 2006 – REVISED APRIL 2013

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AC Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified

Symbol

Parameter

Conditions

Reference

Min

Typ

Max

Units

Serial Video Data Inputs

SMPTE 259M, Level C

270

SMPTE 259M, Level D

360

Serial Input Data Rate

SMPTE 344M

540

SMPTE 292M

1,483

SDI, SDI

SMPTE 292M

1,485

20%–80%, SMPTE 259M

0.4

1.0

1.5

ns

Data Rates

Rise Time, Fall Time

20%–80%, SMPTE 292M

270

ps

Data Rates

Parallel Video Data Outputs

27.0

36.0

Video Output Clock

54.0

MHz

Frequency

74.176

74.25

Propagation Delay, Video

50%–50%

0.5

2.0

ns

Clock to Video Data Valid

Timing Diagram

Duty Cycle, Video Clock

50±5

%

27MHz

2.0

36MHz

1.4

Video Data Output Clock

Jitter

54MHz

1.0

74.25MHz

0.5

Parallel Ancillary / Control Data Inputs, Multi-function Parallel Bus Inputs

Ancillary / Control Data Clock

MHz

Frequency

Duty Cycle, Ancillary Data

45

50

55

%

Clock

Output Rise Time, Fall Time

10%–90%

1.0

1.5

3.0

3.0

1.5

ns

Control Data Input or I/O Bus

Timing Diagram

Input

3.0

1.5

Parallel Ancillary / Control Data Outputs

Propagation Delay, Clock to

8.5

Control Data

50%–50%

ns

Timing Diagram

Propagation Delay, Clock to

11.5

Ancillary Data

Multi-function Parallel I/O Bus

IO0–IO7

Rise Time, Fall Time

10%–90%

1.0

1.5

3.0

ns

Timing Diagram

PLL/CDR, Format Detect

0.32

1.0

Lock Detect Time

0.26

1.0

ms

Format Detect Time

All Rates

20

(1)

(2)

When used to clock control data into or from the LMH0031, the duty cycle restriction does not apply.

(3)

Measured from rising-edge of first SDI cycle until Lock Detect bit goes high (true). Lock time includes CDR phase acquisition time plus

PLL lock time.

8

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