TFP501

SLDS127C

– JULY 2001 – REVISED JULY 2011

www.ti.com

AC ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Differential input sensitivity

(1)

150

Maximum differential input

1560

Analog input intra-pair (+ to

–) differential skew

(2)

(3)

ns

Analog input intra-pair or channel to channel

(4)

ns

skew

(2)

Worst case differential input clock jitter tolerance

(5)

112 MHz, 1 pixel/clock

200

ps

(2)

ST = Low,

1.9

Rise time of data and control signals

(6) (7)

ns

ST = High,

1.9

ST = Low,

1.9

Fall time of data and control signals

(6) (7)

ns

ST = High,

1.9

ST = Low,

1.9

Rise time of ODCK clock

(6)

ns

ST = High,

1.9

Fall time of ODCK clock

(6)

ST = Low,

1.9

ns

ST = High,

1.9

1.2

1 pixel/clock, PIXS = low,

ns

OCK_INV = low

1.2

2 pixel/clock, PIXS = high,

2.7

Setup time, data and control signal to falling edge

STAG = high,

ns

of ODCK

(7)

2.7

OCK_INV = low

2 pixel and STAG

1.7

PIXS = high, STAG = low,

ns

1.7

OCK_INV = low

0.9

1 pixel/clock, PIXS = low,

ns

OCK_INV = low

0.9

Hold time, data and control signal to falling edge of

ODCK

(7)

2 pixel and STAG,

2.9

PIXS = high, STAG = low,

ns

2.9

OCK_INV = low

1 pixel/clock, PIXS = low,

1.9

ns

OCK_INV = high

1.9

2 pixel/clock, PIXS = high,

2.9

STAG = high,

ns

Setup time, data and control signal to rising edge of

2.9

OCK_INV = high

ODCK

(7)

2 pixel and STAG,

2.0

PIXS = high,

ns

2.0

STAG = low,

OCK_INV = high

1 pixel/clock, PIXS = low,

0.5

ns

OCK_INV = high

0.5

Hold time, data and control signal to rising edge of

ODCK

(7)

2 pixel and STAG,

1.4

PIXS = high, STAG = Low,

ns

1.4

OCK_INV = high

PIX = Low

25

165

ODCK frequency

MHz

PIX = High

12.5

82.5

ODCK duty-cycle

45%

50%

60%

Propagation delay time from PD low to Hi-Z outputs

18

ns

Propagation delay time from PDO low to Hi-Z

18

ns

outputs

Time between DE transition to SCDT low

(8)

165 MHz

25

ms

Time between DE low to SCDT high

(8)

8

(9)

ODCK latching edge to QE[23:0] data output

STAG = Low, PIXS = High

ns

(1)

Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection.

(2)

By characterization

(3)

(4)

when in 2-pixel/clock mode.

(5)

Measured differentially at 50% crossing using ODCK output clock as trigger.

(6)

Rise and fall times measured as time between 20% and 80% of signal amplitude.

(7)

Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1]

(8)

Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.

(9)

8

Copyright

© 2001–2011, Texas Instruments Incorporated