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TFP501PZP Datasheet(PDF) 13 Page - Texas Instruments |
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TFP501PZP Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 24 page ![]() _ + Internal Termination at 50 Ω AVCC DVI-Compliant Cable DATA DATA TI TFP501 Receiver TI TFP510 Transmitter Current Source 1/2 VID AVCC AVCC - 1/2 VID + 1/2 VID - 1/2 VID VID a ) Single-Ended Input Signal b) Differential Input Signal TFP501 www.ti.com SLDS127C – JULY 2001 – REVISED JULY 2011 TFP501 TMDS INPUT LEVELS AND INPUT IMPEDANCE MATCHING The TMDS inputs to the TFP501 receiver have a fixed single-ended input termination impedance to AVDD. The TFP501 is internally optimized using a laser trim process to precisely fix the single-ended termination impedance at 50 Ω. This fixed impedance eliminates the need for external termination resistors while providing optimum impedance matching to standard DVI cables having a characteristic impedance of 100 Ω. Figure 14 shows a conceptual schematic of a TFP510 transmitter and TFP501 receiver connection. The TFP510 transmitter drives the twisted-pair cable via a current source, usually achieved with an open-drain type output driver. The internal single-ended termination resistors, which are matched to the characteristic impedance of the DVI cable, provide a pullup to AVDD. Naturally, when the transmitter is disconnected and the TFP501 DVI inputs are left unconnected, the TFP501 receiver inputs are pulled up to AVDD. The single-ended differential signal and full differential signal is shown in Figure 15. The TFP501 is designed to respond to differential signal swings ranging from 150 mV to 1.56 V with common mode voltages ranging from (AVDD–300 mV) to (AVDD–37 mV). Figure 14. TMDS Differential Input and Transmitter Connection Figure 15. TMDS Inputs TFP501 MODES OF OPERATION The TFP501 provides system design flexibility and value by providing the system designer with configurable options or modes of operation to support varying system architectures. The following table outlines the various panel modes that can be supported along with appropriate external control pin settings. PANEL PIXEL RATE ODCK LATCH EDGE ODCK DFO PIXS OCK_INV TFT or 16-bit DSTN 1 pixel/clock Falling Free run 0 0 0 TFT or 16-bit DSTN 1 pixel/clock Rising Free run 0 0 1 TFT 2 pixel/clock Falling Free run 0 1 0 TFT 2 pixel/clock Rising Free run 0 1 1 24-bit DSTN 1 pixel/clock Falling Gated low 1 0 0 NONE 1 pixel/clock Rising Gated low 1 0 1 Copyright © 2001–2011, Texas Instruments Incorporated 13 |
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