| Electronic Components Datasheet Search |
|
STA400A Datasheet(PDF) 95 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STA400A Datasheet(HTML) 95 Page - STMicroelectronics |
|
95 / 117 page ![]() 95/117 STA400A b7: Sat2 Lock indicator interrupt masked 0=disabled; 1=enabled. b6: Sat1 Lock indicator interrupt masked 0=disabled; 1=enabled. b5: MFP_CLK interrupt masked (5 msec impulse sync) 0=disabled; 1=enabled. b4: MFP_CLK interrupt masked (level) 0=disabled; 1=enabled. b3: IIC-bus illegal address masked 0=disabled; 1=enabled. b2: TDM interrupt masked 0=disabled; 1=enabled. b1: FEC interrupt masked 0=disabled; 1=enabled. b0: MCM interrupt masked 0=disabled; 1=enabled. Note: bit5 and bit4 cannot be used togheter, i.e. if bit5 is used the bit4 must be masked and viceversa. If both are enabled, bit4 will be sent to INTR pin. IRQ1_STATUS - Interrupt Status Register This register represents the interrupt vector when the INTR pin is activated (HIGH level active). It can be reset after read if the bit0 (IRQ_RST_CTRL) of the CONTROL register is set to ‘1’ or a single bit can be reset directly writing ‘0’. b7: Interrupt request from Sat2 lock indicator (high active); b6: Interrupt request from Sat1 lock indicator (high active); b5: Interrupt request from MFP_CLK (5 msec impulse continuos sync signal); Bit5 is generated from the MFP_CLK and is a 432msec period signal with ~1.16% duty-cycle (5msec/432msec); there is no need to reset bit5 by the interrupt routine. b4: Interrupt request from MFP_CLK (high active). Bit4 is activated by the positive edge of the MFP_CLK and is a high level signal; the interrupt routing must reset this bit. b3: Interrupt request from IIC-bus illegal address (high active); b2: Interrupt request from TDM (high active); b1: Interrupt request from FEC (high active); b0: Interrupt request from MCM (high active). STATUS1 - CDEC Status Register This register represents the interrupt vector when the INTR pin is activated (HIGH level active). It can be reset after read if the bit0 (IRQ_RST_CTRL) of the CONTROL register is set to ‘1’ or a single bit can be reset directly writing ‘0’. b7-b4: Reserved for Future Use Type: SingleByte - PR Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex) IRQ1_STATUS 0419 7-0 00 Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex) STATUS1 041F 7-0 -- |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |