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TMS320C6472ECTZ Datasheet(PDF) 181 Page - Texas Instruments |
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TMS320C6472ECTZ Datasheet(HTML) 181 Page - Texas Instruments |
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181 / 269 page  10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop SDA SCL 1 11 9 TMS320C6472 www.ti.com SPRS612G – JUNE 2009 – REVISED JULY 2011 7.12.3 I2C Electrical Data/Timing Table 7-51. Timing Requirements for I2C Input(1) (see Figure 7-39) 500/625/700 NO. STANDARD MODE FAST MODE UNIT MIN MAX MIN MAX 1 tc(SCL) Cycle time, SCL 10 2.5 μs Setup time, SCL high before SDA low (for a 2 tsu(SCLH-SDAL) 4.7 0.6 μs repeated START condition) Hold time, SCL low after SDA low (for a 3 th(SCLL-SDAL) 4 0.6 μs START and a repeated START condition) 4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 μs 5 tw(SCLH) Pulse duration, SCL high 4 0.6 μs 6 tsu(SDAV-SDLH) Setup time, SDA valid before SCL high 250 100(2) ns Hold time, SDA valid after SCL low (For I2C 7 th(SDA-SDLL) 0(3) 0(3) 0.9(4) μs bus ™ devices) Pulse duration, SDA high between STOP and 8 tw(SDAH) 4.7 1.3 μs START conditions 9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb (5) 300 ns 10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb (5) 300 ns 11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb (5) 300 ns 12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb (5) 300 ns Setup time, SCL high before SDA high (for 13 tsu(SCLH-SDAH) 4 0.6 μs STOP condition) 14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns 15 Cb (5) Capacitive load for each bus line 400 400 pF (1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. (2) A Fast-mode I2C-bus ™ device can be used in a Standard-mode I2C-bus™ system, but the requirement tsu(SDA-SCLH) ≥250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. (3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. (5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Figure 7-39. I2C Input Timing Copyright © 2009–2011, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 181 Submit Documentation Feedback Product Folder Link(s) :TMS320C6472 |
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