TMS320C6472ECTZ datasheet(185/269 Pages) TI1

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TMS320C6472

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SPRS612G

– JUNE 2009 – REVISED JULY 2011

Table 7-55. Switching Characteristics Over Recommended Operating Conditions for

Host-Port Interface Cycles(1)(2)(3)

(see Figure 7-41 through Figure 7-44)

500/625/700

NO.

PARAMETER

UNIT

MIN

MAX

Case 1. HPIC or HPIA read

Case 2. HPID read with no

17 * M + 20

auto-increment

Delay time, HSTROBE low to

Case 3. HPID read with auto-increment

td(HSTBL-HDV)

16 * M + 20

DSP data valid

and read FIFO initially empty

Case 4. HPID read with auto-increment

and data previously prefetched into the

read FIFO

tdis(HSTBH-HDV)

Disable time, HD high-impedance from HSTROBE high

ten(HSTBL-HD)

Enable time, HD driven from HSTROBE low

td(HSTBL-HRDYH)

Delay time, HSTROBE low to HRDY high

td(HSTBH-HRDYH)

Delay time, HSTROBE high to HRDY high

Case 1. HPID read with no

18 * M + 20

auto-increment

Delay time, HSTROBE low to

td(HSTBL-HRDYL)

HRDY low

Case 2. HPID read with auto-increment

17 * M + 20

and read FIFO initially empty

td(HDV-HRDYL)

Delay time, HD valid to HRDY low

Case 1. HPIA write

5 * M + 20

Delay time, HSTROBE high to

td(DSH-HRDYL)

Case 2. HPID write with no

HRDY low

5 * M + 20

auto-increment

Delay time, HSTROBE low to HRDY low for HPIA write and FIFO not

td(HSTBL-HRDYL)

40 * M + 20

empty

td(HASL-HRDYH)

Delay time, HAS low to HRDY high

(1)

M = HPI module clock period = 6 * CPU clock period or 12 ns at 500 MHz. (This duration will be much longer when PLL1 is in bypass

mode.)

(2)

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(3)

Maximum delays for 1 (cases 2 and 3), 6, 34, and 35 assume no conflict with SCR. The true maximum delay during application

execution is dependent on internal congestion delays. HRDY must be used to guarantee valid cycle completion.

C64x+ Peripheral Information and Electrical Specifications

185

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