TMS320C6472ECTZ datasheet(183/269 Pages) TI1

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TMS320C6472

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SPRS612G

– JUNE 2009 – REVISED JULY 2011

7.13 Host-Port Interface (HPI) Peripheral

7.13.1 HPI Device-Specific Information

The C6472 device includes a user-configurable 16-bit host-port interface (HPI16).

A host processor uses HPI to access internal registers and C6472 memory or external memory through

the C6472 DDR2 EMIF. This accessibility may be useful for initializing the device in connection with the

host boot mode and reading internal memory in connection with a software failure. Software handshaking,

via the HRDY bit of the HPI control register (HPIC), is not supported on the C6472 device. For details

about the HPI registers and their modes, see the TMS320C6472/TMS320TCI6486 DSP Host Port

Interface (HPI) User's Guide (literature number SPRUEG1).

7.13.2 HPI Peripheral Register Descriptions

Table 7-53 discusses access to the HPI registers from the C6472 C64x+ megamodules.

Table 7-53. HPI Control Registers

HEX ADDRESS RANGE

ACRONYM

COMMENTS

0288 0000

HPIPID

HPI Peripheral ID Register

PWREMU_MGMT has both

0288 0004

PWREMU_MGMT

HPI Power and Emulation Management Register

Host/CPU read/write access.

0288 0008 - 0288 002C

Reserved

The Host has read/write

access to the HPIC register.

0288 0030

HPIC

HPI Control Register

The CPU has primarily read

access to the HPIC

0288 0034

HPID

Data register

The Host has read/write

access to the HPIA registers.

The CPU has only read

0288 0038

HPIAR/HPIAW(2)

HPI Address Registers

access to the HPIA registers.

0288 003C - 0289 FFFC

Reserved

(1)

The CPU can write 1 to the HINT bit to generate an interrupt to the host and it can write 1 to the DSPINT bit to clear/acknowledge an

interrupt from the host.

(2)

There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that

HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the

perspective of the host. The CPU can access HPIAW and HPIAR independently. For details about the HPIA registers and their modes,

see the TMS320C6472/TMS320TCI6486 DSP Host Port Interface (HPI) User

's Guide (literature number SPRUEG1).

7.13.3 Host Access to HPI

The host-port interface pins comprise a multiplexed access to the HPI module that contains the registers

described in Table 7-53. This external interface can only directly access the HPIC, HPID, and the two

HPIA registers. The select lines, HCNTL[1:0], are used to determine which of these registers is being

accessed. The remaining control lines, HR/W and HHWIL, qualify the external accesses and the strobes,

HCS, HDS1, and HDS2, latch data into the HPI registers. Optionally, HAS can be used to latch the select

and control inputs.

Write and read accesses to these HPI registers initiate DMA-like transfers within the DSP. The HRDY

(host ready) output from the HPI must be monitored to determine when a requested access is complete

before initiating the next access. Since the HPI module operates on the CPU/6 clock, these access cycles

are slow when PLL1 is in bypass mode; i.e., at the beginning of host boot mode. HPI accesses are used

to configure PLL1 to shorten these cycles.

C64x+ Peripheral Information and Electrical Specifications

183

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