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MCP19110T-E/MJ Datasheet(PDF) 3 Page - Microchip Technology |
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MCP19110T-E/MJ Datasheet(HTML) 3 Page - Microchip Technology |
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3 / 226 page  2013-2016 Microchip Technology Inc. DS20002331D-page 3 MCP19110/11 TABLE 1: 24-PIN SUMMARY I/O Basic Additional GPA0 1 Y AN0 — — IOC Y — Analog Debug Output (1) GPA1 2 Y AN1 — — IOC Y — Sync. Signal In/Out (2, 3) GPA2 3 Y AN2 T0CKI — IOC INT Y — — GPA3 5 Y AN3 — IOC Y — — GPA4 8 N — — — IOC N — — GPA5 7 N — — — IOC(4) Y(5) MCLR — GPA6 6 N — — — IOC N ICSPDAT — GPA7 5 N — — SCL IOC N ICSPCLK — GPB0 9 N — — SDA IOC N — — GPB1 23 Y AN4 — — IOC Y — Error Signal In/Out (3) GPB2 24 Y AN5 — — IOC Y — — VIN 11 N — — — — — VIN Device Input Voltage VDR 14 N — — — — — VDR Gate Drive Supply Input Voltage VDD 18 N — — — — — VDD Internal Regulator Output GND 10 N — — — — — GND Small Signal Ground PGND 12 N — — — — — — Large Signal Ground LDRV 13 N — — — — — — Low-Side MOSFET Connection HDRV 16 N — — — — — — High-Side MOSFET Connection PHASE 15 N — — — — — — Switch Node BOOT 17 N — — — — — — Floating Bootstrap Supply +VSEN 21 N — — — — — — Output Voltage Differential Sense -VSEN 22 N — — — — — — Output Voltage Differential Sense +ISEN 20 N — — — — — — Current Sense Input -ISEN 19 N — — — — — — Current Sense Input Note 1: The Analog Debug Output is selected when the ATSTCON<BNCHEN> bit is set. 2: Selected when device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0> bits in the BUFFCON register. 3: Selected when device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bits in the BUFFCON register. 4: The IOC is disabled when MCLR is enabled. 5: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control. |
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