MCP2221AT-ISLASHST datasheet(53/80 Pages) MICROCHIP

53 / 80 page

 2016 Microchip Technology Inc.

DS20005565A-page 53

MCP2221A

3.1.14.1

Responses

TABLE 3-39:

RESPONSE 1 STRUCTURE

Byte

Index

Function Description

Value

Effect

0x61

Get SRAM Settings – command code echo

0x00

Command completed successfully

Length in bytes of the SRAM Chip

settings area.

Length in bytes of the SRAM GP

settings area.

Bit 7: CDC Serial Number Enumeration

Enable

The USB serial number will be used during the USB

enumeration of the CDC interface

No serial number descriptor will be presented during

the USB enumeration

Bit 6: Initial value for LEDUARTRX pin

option

This value represents the logic level signaled when no

UART RX activity takes places. When the UART RX (of

the MCP2221A) is receiving data, the LEDUARTRX pin

will take the negated value of this bit.

Bit 5: Initial value for LEDUARTTX pin

option.

This value represents the logic level signaled when no

UART TX transmission takes place. When the UART

TX (of the MCP2221A) is sending data, the

LEDUARTTX pin will take the negated value of this bit.

Bit 4: Initial value for LEDI2C pin option

This value represents the logic level signaled when no

I2C traffic occurs. When I2C traffic is active, the LEDI2C

pin (if enabled) will take the negated value of this bit.

Bit 3: Initial value for SSPND pin option

This value represents the logic level signaled when the

device is not in Suspend mode. Upon entering Suspend

mode, the SSPND pin (if enabled) will take the negated

value of this bit.

Bit 2: Initial value for USBCFG pin

option

This value represents the logic level signaled when the

device is not USB configured. When the device will be

USB-configured, the USBCFG pin (if enabled) will take

the negated value of this bit.

Bit 1-0: Chip Configuration security

option

Permanently locked

Password-protected

Unsecured

5Bit 7-5

Don’t

care

Bit 4-0: Clock Output divider value

If the GP pin (exposing the clock output) is enabled for

clock output operation, the divider value will be used on

the 48 MHz USB internal clock and its divided output

will be sent to this pin. (Bits 4-3 for duty cycle and bits

2-0 for the clock divider.)

Bit 7-6: DAC Reference voltage option

Reference voltage is 4.096V

Reference voltage is 2.048V

Reference voltage is 1.024V

Reference voltage is off (this is useful for the case in

which the DAC uses other reference than VRM DAC;

e.g., VDD)

Bit 5: DAC reference option

DAC reference is VRM DAC voltage

DAC reference is VDD

Bit 4-0: Power-up DAC value

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