A3924 datasheet(39/55 Pages) ALLEGRO

39 / 55 page

Automotive, Full-Bridge MOSFET Driver

A3924

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

SERIAL REGISTER INTERFACE

0: Config 0

TOC3 TOC2 TOC1 TOC0

DT5

DT4

DT3

DT2

DT1

DT0

1: Config 1

OCT3 OCT2 OCT1 OCT0

VTL5

VTL4

VTL3

VTL2

VTL1

VTL0

* Power-on-reset value shown below each input register bit.

Config 0

TOC[3:0] – OVERCURRENT VERIFICATION TIME

tOCQ = n × 500 ns

where n is a positive integer defined by TOC[3:0]. For example,

for the power-on-reset condition TOC[3:0] = [1111], then tOCQ =

7.5 µs.

The range of tOCQ is 0 to 7.5 µs.

DT[5:0] – DEAD TIME

tDEAD = n × 50 ns

where n is a positive integer defined by DT[5:0]. For example,

for the power-on-reset condition DT[5:0] = [10 0000], then tDEAD

= 1.6 µs.

The range of tDEAD is 100 ns to 3.15 µs. Selecting a value of 1

or 2 will set the dead time to 100 ns. A value of zero disables the

dead time.

P – PARITY BIT

Ensures an odd number of 1s in any serial transfer.

Config 1

OCT[3:0] – OVERCURRENT THRESHOLD

VOCT = (n + 1) × 300 mV

where n is a positive integer defined by OCT[3:0]. For example,

for the power-on-reset condition OCT[3:0] = [1001], then VOCT =

3 V.

The range of VOCT is 0.3 to 4.8 V.

VTL[5:0] – LOW-SIDE VDS OVERVOLTAGE THRESHOLD

VDSTL = n × 50 mV

where n is a positive integer defined by VTL[5:0]. For example,

for the power-on-reset condition VTL[5:0] = [01 1000], then

VDSTL = 1.2 V.

The range of VDSTL is 0 to 3.15 V.

P – PARITY BIT

Ensures an odd number of 1s in any serial transfer.

Serial Register Reference*

A3924 Datasheet(PDF) 39 Page - Allegro MicroSystems

A3924 Datasheet(HTML) 39 Page - Allegro MicroSystems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Datasheet Download

Link URL