A3924 datasheet(21/55 Pages) ALLEGRO

21 / 55 page

Automotive, Full-Bridge MOSFET Driver

A3924

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

DIAGNOSTIC MONITORS

Multiple diagnostic features provide three levels of fault monitor-

ing. These include critical protection for the A3924, monitors for

operational voltages and states, and detection of power bridge

and load fault conditions. All diagnostics, except for POR, serial

transfer error and overtemperature can be masked by setting the

appropriate bit in the mask registers.

Except for the two phase state outputs, the fault status is available

from two sources, the DIAG output terminal and the status and

diagnostic registers accessed through the serial interface.

DIAG Diagnostic Output

The DIAG terminal is a single diagnostic output signal that can

be programmed by setting the contents of the DG[1:0] variable

through the serial interface to provide one of three dedicated

diagnostic signals:

• DG = 0: a general fault flag

• DG = 1: a pulsed fault flag

• DG = 2: a voltage representing the temperature of the internal

silicon

• DG = 3: the sense amplifier output offset voltage

At power-up, or after a power-on-reset, the DIAG terminal

outputs a general logic-level fault flag which will be active-low

if a fault is present. This fault flag remains low while the fault is

present or if one of the latched faults has been detected and the

outputs disabled. When the general fault flag is reset the DIAG

output will be high.

The pulsed fault output option provides a continuous low-

frequency low-duty cycle pulsed output when a fault is present

or if one of the latched faults has been detected and the outputs

disabled. When the general fault flag is reset and no fault is

present, the signal output on the DIAG terminal is continuous

low-frequency, high-duty cycle pulses. The period of the DIAG

signal in pulsed mode is defined by tFP and is typically 100 ms.

The two duty cycles are defined by DFP and are typically 20%

when a fault is present and 80% when no fault is present.

0.8 t

0.2 t

DIAG: No Fault

DIAG: Fault

Figure 6: DIAG – Pulsed Output Mode

The temperature output option provides access to the internal

voltage representing the surface temperature of the silicon.

The sense amplifier option provides the output offset voltage,

(VOOS) of the sense amplifier, defined by the contents of the

SAO[3:0] bits in configuration register 5.

Diagnostic Registers

The serial interface allows detailed diagnostic information to be

read from the diagnostic registers on the SDO output terminal at

any time.

A system Status register provides a summary of all faults in a

single read transaction. The Status register is always output on

SDO when any register is written.

Table 4: Diagnostic Functions

Name

Diagnostic

Level

POR

Internal logic supply undervoltage causing power-

on reset

Chip

Chip junction overtemperature

Chip

Serial transmission error

Chip

High chip junction temperature warning

Monitor

VSO

VBB supply overvoltage (Load dump detection)

Monitor

VSU

VBB supply undervoltage

Monitor

VLO

Logic terminal overvoltage

Monitor

ETO

ENABLE watchdog timeout

Monitor

VRO

VREG output overvoltage

Monitor

VRU

VREG output undervoltage

Monitor

V3U

V3 Regulator output undervoltage

Monitor

V3O

V3 Regulator output overvoltage

Monitor

AHU

A high-side VGS undervoltage

Monitor

ALU

A low-side VGS undervoltage

Monitor

BHU

B high-side VGS undervoltage

Monitor

BLU

B low-side VGS undervoltage

Monitor

OCA

Overcurrent on phase A

Bridge

OCB

Overcurrent on phase B

Bridge

Open load

Bridge

Bootstrap undervoltage phase A

Bridge

Bootstrap undervoltage phase B

Bridge

AHO

Phase A high-side VDS overvoltage

Bridge

ALO

Phase A low-side VDS overvoltage

Bridge

BHO

Phase B high-side VDS overvoltage

Bridge

BLO

Phase B low-side VDS overvoltage

Bridge

A3924 Datasheet(PDF) 21 Page - Allegro MicroSystems

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