ST72561 datasheet(199/262 Pages) STMICROELECTRONICS

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ST72561

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beCAN CONTROLLER (Cont’d)

TRANSMIT ERROR COUNTER REG. (TECR)

Read Only

Reset Value: 00h

TEC[7:0] is the least significant byte of the 9-bit

Transmit Error Counter implementing part of the

fault confinement mechanism of the CAN protocol.

RECEIVE ERROR COUNTER REG. (RECR)

Page: 00h — Read Only

Reset Value: 00h

REC[7:0] is the Receive Error Counter implement-

ing part of the fault confinement mechanism of the

CAN protocol. In case of an error during reception,

this counter is incremented by 1 or by 8 depending

on the error condition as defined by the CAN stand-

ard. After every successful reception the counter is

decremented by 1 or reset to 120 if its value was

higher than 128. When the counter value exceeds

127, the CAN controller enters the error passive

state.

CAN DIAGNOSIS REGISTER (CDGR)

All bits of this register are set and clear by soft-

ware.

Read / Write

Reset Value: 0000 1100 (0Ch)

Bit 3 = RX CAN Rx Signal

- Read

Monitors the actual value of the CAN_RX Pin.

Bit 2 = SAMP Last Sample Point

- Read

The value of the last sample point.

Bit 1 = SILM Silent Mode

- Read/Set/Clear

0: Normal operation

1: Silent Mode

Bit 0 = LBKM Loop Back Mode

- Read/Set/Clear

0: Loop Back Mode disabled

1: Loop Back Mode enabled

CAN BIT TIMING REGISTER 0 (CBTR0)

This register can only be accessed by the software

when the CAN hardware is in configuration mode.

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7:6 SJW[1:0] Resynchronization Jump Width

These bits define the maximum number of time

quanta the CAN hardware is allowed to lengthen

or shorten a bit to perform the resynchronization.

Resynchronization Jump Width = (SJW+1).

Bit 5:0 BRP[5:0] Baud Rate Prescaler

These bits define the length of a time quantum.

tq = (BRP+1)/fCPU

For more information on bit timing, please refer to

Section 10.9.4.6 "Bit Timing".

CAN BIT TIMING REGISTER 1 (CBTR1)

Read / Write

Reset Value: 0001 0011 (23h)

Bit 7 = Reserved. Forced to 0 by hardware.

Bit 6:4 BS2[2:0] Time Segment 2

These bits define the number of time quanta in

Time Segment 2.

Time Segment 2=(BS2+1)

TEC7

TEC6

TEC5

TEC4

TEC3

TEC2

TEC1

TEC0

REC7

REC6

REC5

REC4

REC3

REC2

REC1

REC0

SAMP

SILM

LBKM

SJW1

SJW0

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

BS22

BS21

BS20

BS13

BS12

BS11

BS10

ST72561 Datasheet(PDF) 199 Page - STMicroelectronics

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