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ST72561 Datasheet(PDF) 203 Page - STMicroelectronics |
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ST72561 Datasheet(HTML) 203 Page - STMicroelectronics |
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203 / 262 page ![]() ST72561 203/262 beCAN CONTROLLER (Cont’d) MAILBOX DATA LENGTH CONTROL REGIS- TER (MDLC) All bits of this register is write protected when the mailbox is not in empty state. Read / Write Reset Value: xxxx xxxx (xxh) Bit 7 = Reserved, must be kept cleared. 6:4 = Reserved, forced to 0 by hardware. Bit 3:0 = DLC[3:0] Data Length Code This field defines the number of data bytes a data frame contains or a remote frame request. MAILBOX DATA REGISTERS (MDAR[7:0]) All bits of this register are write protected when the mailbox is not in empty state. Read / Write Reset Value: Undefined Bit 7:0 = DATA[7:0] Data A data byte of the message. A message can con- tain from 0 to 8 data bytes. 70 0000 DLC3 DLC2 DLC1 DLC0 70 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 |
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