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ST72561 Datasheet(PDF) 206 Page - STMicroelectronics |
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ST72561 Datasheet(HTML) 206 Page - STMicroelectronics |
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206 / 262 page ![]() ST72561 206/262 beCAN CONTROLLER (Cont’d) CAN FILTER MODE REGISTER (CFMR1) All bits of this register are set and cleared by soft- ware. Read / Write Reset Value: 0000 0000 (00h) Bit 7:4 = Reserved. Forced to 0 by hardware. Bit 3 = FMH5 Filter Mode High Mode of the high registers of Filter 5. 0: High registers are in mask mode 1: High registers are in identifier list mode Bit 2 = FML5 Filter Mode Low Mode of the low registers of filter 5. 0: Low registers are in mask mode 1: Low registers are in identifier list mode Bit 1 = FMH4 Filter Mode High Mode of the high registers of filter 4. 0: High registers are in mask mode 1: High registers are in identifier list mode Bit 0 = FML4 Filter Mode Low Mode of the low registers of filter 4. 0: Low registers are in mask mode 1: Low registers are in identifier list mode FILTER x REGISTER[7:0] (CFxR[7:0]) Read / Write Reset Value: Undefined In all configurations: Bit 7:0 = FB[7:0] Filter Bits Identifier Each bit of the register specifies the level of the corresponding bit of the expected identifier. 0: Dominant bit is expected 1: Recessive bit is expected Mask Each bit of the register specifies whether the bit of the associated identifier register must match with the corresponding bit of the expected identifier or not. 0: Don’t care, the bit is not used for the comparison 1: Must match, the bit of the incoming identifier must have the same level has specified in the corresponding identifier register of the filter. Note: Each filter x is composed of 8 registers, CFxR[7:0]. Depending on the scale and mode configuration of the filter the function of each reg- ister can differ. For the filter mapping, functions description and mask registers association, refer to Section 10.9.4.3Identifier Filtering. A Mask/Identifier register in mask mode has the same bit mapping as in identifier list mode. Note: To modify these registers, the correspond- ing FACT bit in the CFCR register must be cleared. 70 0 0 0 0 FMH5 FML5 FMH4 FML4 70 FB7 FB6 FB5 FB4 FB3 FB2 FB1 FB0 |
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