ST72561 datasheet(201/262 Pages) STMICROELECTRONICS

201 / 262 page

ST72561

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beCAN CONTROLLER (Cont’d)

10.9.8.2 Mailbox Registers

This chapter describes the registers of the transmit

and receive mailboxes. Refer to Section 10.9.4.4

"Message Storage" for detailed register mapping.

Transmit and receive mailboxes have the same

registers except:

– MCSR register in a transmit mailbox is replaced

by MFMI register in a receive mailbox.

– A receive mailbox is always write protected.

– A transmit mailbox is write enable only while

empty, corresponding TME bit in the CTPR reg-

ister set.

MAILBOX CONTROL STATUS REGISTER

(MCSR)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = Reserved. Forced to 0 by hardware.

Bit 5 = TERR Transmission Error

- Read

This bit is updated by hardware after each trans-

mission attempt.

0: The previous transmission was successful

1: The previous transmission failed due to an error

Bit 4 = ALST Arbitration Lost

- Read

This bit is updated by hardware after each trans-

mission attempt.

0: The previous transmission was successful

1: The previous transmission failed due to an arbi-

tration lost

Bit 3 = TXOK Transmission OK

- Read

The hardware updates this bit after each transmis-

sion attempt.

0: The previous transmission failed

1: The previous transmission was successful

Note: This bit has the same value as the corre-

sponding TXOKx bit in the CTSR register.

Bit 2 = RQCP Request Completed

- Read/Clear

Set by hardware when the last request (transmit or

abort) has been performed.

Cleared by software writing a “1” or by hardware

on transmission request.

Note: This bit has the same value as the corre-

sponding RQCPx bit of the CTSR register.

Clearing this bit clears all the status bits (TX-

OK, ALST and TERR) in the MCSR register and

the RQCP and TXOK bits in the CTSR register.

Bit 1 = ABRQ Abort Request for Mailbox

- Read/Set

Set by software to abort the transmission request

for the corresponding mailbox.

Cleared by hardware when the mailbox becomes

empty.

Setting this bit has no effect when the mailbox is

not pending for transmission.

Bit 0 = TXRQ Transmit Mailbox Request

- Read/Set

Set by software to request the transmission for the

corresponding mailbox.

Cleared by hardware when the mailbox becomes

empty.

Note: This register is implemented only in transmit

mailboxes. In receive mailboxes, the MFMI regis-

ter is mapped at this location.

TERR

ALST

TXOK RQCP ABRQ TXRQ

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