AFE1302

5

SBWS014

THEORY OF OPERATION

The AFE1302 consists of a transmit (TX) channel, a receive

(RX) channel, and a digital interface to connect to an ADSL

DSP. In addition, VCXO circuitry and a VCXO control

DAC are included for precise clock generation.

The TX channel receives digital data at the nominal rate of

1.104MWords/s to 8.832MWords/s. These TX data words

are interpolated up to the AFE1302 clock rate of 35.328MHz.

The data is converted to analog form with a 16-bit delta-

sigma DAC and bandwidth limited with a fourth-order,

switched-capacitor low-pass filter. The filter output is buff-

ered and drives off-chip to an external Burr-Brown line-

driver circuit from Texas Instruments. This line driver is

configured as an LC passive filter to provide additional out-

of-band noise and distortion attenuation (see System sec-

tion). Transmit power can be reduced with a combination of

digital and analog attenuation to ensure compliance with the

G.992.2 “politeness” rule.

In the RX channel, the analog receive signal is input to a PGA.

The output of the first-order, switched capacitor filter is digi-

tized with a 16-bit delta-sigma ADC. A decimation filter

ensures a compliant word rate (1.104MWords/s to

8.832MWords/s) to the ADSL digital chip.

Precise phase alignment is required to ensure proper opera-

tion of the ADSL modem. The active circuitry required to

create a VCXO is included on the AFE1302. This includes

the gain element as well as a 10-bit, monotonic DAC. The

only external components required are a varactor, load

capacitor, and crystal.

TX DISTORTION AND NOISE REQUIREMENTS

The TX output is a DMT signal generated by the AFE1302.

This output contains the desired DMT signal in the TX

frequency band as well as unwanted noise and distortion in

both the TX and RX frequency bands. The inband TX

distortion and noise is specified by the MultiTone Power

Ratio (MTPR) test. Since MTPR is better than 70 dB, full-

rate ADSL performance is guaranteed for TX upstream

signals.

However, TX distortion and noise can also limit down-

stream RX performance. TX noise and distortion can de-

grade RX signal quality since the TX output is connected to

the RX input through filters, line driver, and hybrid. Three

tests show out-of-band TX performance as used in the

ADSL system. Total harmonic distortion (THD) shows the

overall linearity of the TX signals. The next test uses a

typical ADSL DMT TX signal and measures the largest

distortion tone in the RX band. The largest distortion tone in

the RX band is –98 dBVrms or –124 dBm/Hz as measured

in a 4.3125 kHz bandwidth. In the last test, TX noise is

measured by transmitting no signal. Noise as shaped by the

TX filter is lower than –116dBm/Hz in the RX band.

Data is transmitted to the DSP from the AFE1302 on the

RX[0:3] lines, as shown in Figure 1. The Data RX[0:3]

changes during the rising edge of CLKM within the AFE,

and the Data are valid on the falling edge of CLKM for the

DSP to read. The minimum setup and hold time are 5ns (see

Figure 2); the start of a new sample is indicated by CLWD

being HIGH.

During normal operation, a 16-bit TX data word is generated

by the DSP. This TX data is sent from the DSP to the AFE

via four serial lines TX[0:3]. Each serial line is clocked by

CLKM at 35.328MHz or by CLKNIB at 35.328MHz di-

vided by N. CLKNIB and CLWD can be changed by

programming N via the control register.

The RX word output rate and TX word input rate can be

changed by programming N in the control register for values

of 1, 2, 4, or 8. For instance, setting N = 1 sets the TX and

RX data word rate to 8.832Mwords/s.

FIGURE 1. AFE1302/DSP Interface.

ADSL DSP

AFE1302

4

TX[0:3]

RX[0:3]

CLWD

CLKNIB

CLKM

CTRLIN

Control

Register

÷4N

4

÷N

NOTE: N = 1, 2, 4, 8 set by control register.

To insure that TX distortion and noise do not degrade the

RX downstream performance, external filtering and trans-

hybrid loss of greater than 30dB is required. Refer to

Figure 6 for an external circuit and contract TI for a detailed

reference design document.

DIGITAL DATA TRANSMISSION

Data is transmitted to the AFE1302 from the DSP on the

TX[0:3] lines, as shown in Figure 1. The Data TX[0:3]

changes during the rising edge of CLKM within the DSP,

and the Data are valid on the falling edge of CLKM for the

AFE to read. The minimum setup and hold time are 5ns (see

Figure 2); the start of a new sample is indicated by CLWD

being HIGH.