AFE1302

8

SBWS014

M

L

S

S

B

B

REGISTER DESCRIPTIONS

15 14 13

12

11

10

98

7

6543

2

1

0

RX REGISTER

0

X

0

0

0

External Gain Control GC1 (1 Bit)

0

X

0

0

0

External Gain Control GC0 (1 Bit)

0

0

0

0

0

0

0

0

0

0

AGC RX Gain Setting –6dB (6 Bits)

0

0

0

0

0

0

1

0

0

0

AGC RX Gain Setting –5dB (6 Bits)

0

X

X

X

X

X

X

0

0

0

AGC RX Gain Setting X dB (6 Bits)

0

1

0

1

1

1

0

0

0

0

AGC RX Gain Setting 40dB (6 Bits)

0

X

0

0

0

X = 1, Filter Setting 1.1MWords/s; X = 0, Filter Setting 8.8MWords/s

0

0

0

0

0

0

0

Reserved, Must Be Set As Shown

15 14 13

12

11

10

98

7

6543

2

1

0

TX REGISTER

0

0

0

0

0

0

0

0

1

Transmit Attenuator Setting = 0dB (5 Bits)

0

0

0

0

0

1

0

0

1

Transmit Attenuator Setting = –1dB (5 Bits)

0

X

X

X

X

X

0

0

1

Transmit Attenuator Setting = X dB (5 Bits)

0

1

1

1

1

1

0

0

1

Transmit Attenuator Setting = –31dB (5 Bits)

0

X

0

0

1

GP2 (General-Purpose Output 2)

0

X

0

0

1

GP1 (General-Purpose Output 1)

0

X

0

0

1

GP0 (General-Purpose Output 0)

0

X

0

0

1

X = 1, RX and TX Data Format Has 1 Sign Bit and 15 Data Bits

X = 0, RX and TX Data Format Has 2 Sign Bits and 14 Data Bits

0

0

0

1

0

0

1

Reserved, Must Be Set As Shown

15 14 13

12

11

10

98

7

6543

2

1

0

AFE REGISTER

0

X

0

1

0

Digital Loopback TX to RX Through Digital Section (1 Bit)

X = 1, Loopback Mode; X = 0, Normal Operation Mode

0

X

0

1

0

Analog Loopback TX to RX Through Analog Section (1 Bit)

X = 1, Loopback Mode; X = 0, Normal Operation Mode

0

X

0

1

0

X = 1, RX Enable Mode

0

X

X

0

1

0

Data Word Clock Divider (2 Bits)

0

0

0

0

1

0

Data Word Clock = 8.832MHz (2 Bits)

0

0

1

0

1

0

Data Word Clock = 4.416MHz (2 Bits)

0

1

0

0

1

0

Data Word Clock = 2.208MHz (2 Bits)

0

1

1

0

1

0

Data Word Clock = 1.104MHz (2 Bits)

0

X

0

1

0

Clear CLIP Signal: X = 1, RX is Clipping; X = 0, CLIP Cleared

0

0

0

1

0

0

1

0

1

0

Reserved, Must Be Set As Shown

15 14 13

12

11

10

98

7

6543

2

1

0

VCXO DAC VALUE REGISTER

0

X

X

X

X

X

X

X

X

X

X

0

1

1

VCXO DAC Input Word (10 Bits)

0

0

0

0

0

0

0

0

0

0

0

0

1

1

VCXO DAC Input Word = 0 (10 Bits)

0

1

1

1

1

1

1

1

1

1

1

0

1

1

VCXO DAC Input Word = +FS (10 Bits)

0

0

0

0

1

1

Reserved, Must Be Set As Shown

15 14 13

12

11

10

98

7

6543

2

1

0

INTERFACE REGISTER

0

X

X

X

X

X

X

X

X

1

0

0

Reserved

0

X

1

0

0

X = 0, TX[3:0] Should Be Latched On Falling CLKNIB

X = 1, TX[3:0] Should Be Latched On Rising CLKNIB

0

X

1

0

0

X = 0, RX[3:0] Should Be Latched On Falling CLKNIB

X = 1, RX[3:0] Should Be Latched On Rising CLKNIB

0

X

1

0

0

Digital Loopback RX Into TX:

X = 1 Loopback Mode; X = 0 Normal Mode

0

0

1

0

0

Reserved, Must Be Set As Shown

15 14 13

12

11

10

98

7

6543

2

1

0

RESERVED

0

1

111

101

1

1111

1

0

1

Reserved, Must Be Set As Shown

0

X

XXX

XXX

X

XXXX

1

1

0

Reserved, Data ID 6

0

X

XXX

XXX

X

XXXX

1

1

1

Reserved, Data ID 7

NOTE: All registers are initially set to zero.

TABLE V. AFE1302 Control Register.

START

BIT

DATA BITS

DATA ID