TLS810B1 datasheet(9/24 Pages) INFINEON

9 / 24 page

Data Sheet

Rev. 1.0 2015-11-02

TLS810B1LDV50

General Product Characteristics

4.3

Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

Table 3

Thermal Resistance TLS810B1 in PG-TSON-10 Package

Parameter

Symbol

Values

Unit

Note or

Test Condition

Number

Min.

Typ.

Max.

Package Version

Junction to Case1)

1) Not subject to production test, specified by design

RthJC

–

K/W

–

P_4.3.1

Junction to Ambient

RthJA

–60

–

K/W

2s2p board2)

2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm

Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

P_4.3.2

Junction to Ambient

RthJA

–

184

–

K/W

1s0p board, footprint

only3)

3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product

(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).

P_4.3.3

Junction to Ambient

RthJA

–

K/W

1s0p board, 300 mm2

heatsink area on PCB3)

P_4.3.4

Junction to Ambient

RthJA

–

K/W

1s0p board, 600 mm2

heatsink area on PCB3)

P_4.3.5

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