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AS4C64M16D3 Datasheet(PDF) 13 Page - Alliance Semiconductor Corporation

Part # AS4C64M16D3
Description  AS4C64M16D3
PDF  89 Pages
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS4C64M16D3 Datasheet(HTML) 13 Page - Alliance Semiconductor Corporation

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AS4C64M16D3
Confidential
13
Rev. 3.0
Aug. /2014
The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except
DLL reset, and is the minimum time required from an MRS command to a non-MRS command excluding NOP and
DES shown in Figure 7.
Figure 7. tMOD timing
CK#
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
T0
ADDRESS
CK
Tb2
VALID
COMMAND
CKE
Settings
ODT
ODT
ODTLoff + 1
Don't Care
TIME BREAK
VALID
VALID
VALID
MRS
NOP/DES
NOP/DES
NOP/DES
NOP/DES
NOP/DES
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
Old Settings
Updating Settings
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
tMOD
New Settings
RTT_Nom ENABLED prior and/or after MRS command
RTT_Nom DISABLED prior and after MRS command
The mode register contents can be changed using the same command and timing requirements during normal
operation as long as the DRAM is in idle state, i.e., all banks are in the precharged state with tRP satisfied, all data
bursts are completed and CKE is high prior to writing into the mode register. The mode registers are divided into
various fields depending on the functionality and/or modes.



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