EMC1183 datasheet(40/48 Pages) MICROCHIP

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

Revision 1.0 (07-11-13)

SMSC EMC1183

DATASHEET

The Low Limit Status Register contains the status bits that are set when a temperature channel drops

below the low limit. If any of these bits are set, then the LOW status bit in the Status Register is set.

Reading from the Low Limit Status Register will clear all bits. Reading from the register will also clear

the LOW status bit in the Status Register.

The ALERT / THERM2 pin will be set if the programmed number of consecutive alert counts have

been met and any of these status bits are set.

The status bits will remain set until read unless the ALERT / THERM2 pin is configured as a

comparator output (see Section 5.5.2).

Bit 2 - E2LOW - This bit is set when the External Diode 2 channel drops below its programmed low

limit.

Bit 1 - E1LOW - This bit is set when the External Diode 1 channel drops below its programmed low

limit.

Bit 0 - ILOW - This bit is set when the Internal Diode channel drops below its programmed low limit.

6.17

Therm Limit Status Register 37h

The Therm Limit Status Register contains the status bits that are set when a temperature channel

Therm Limit is exceeded. If any of these bits are set, the THERM status bit in the Status Register is

set. Reading from the Therm Limit Status Register will not clear the status bits. Once the temperature

drops below the Therm Limit minus the Therm Hysteresis, the corresponding status bits will be

automatically cleared. The THERM bit in the Status Register will be cleared when all individual channel

THERM bits are cleared.

Bit 2 - E2THERM - This bit is set when the External Diode 2 channel exceeds its programmed Therm

Limit. When set, this bit will assert the THERM pin.

Bit 1 - E1THERM - This bit is set when the External Diode 1 channel exceeds its programmed Therm

Limit. When set, this bit will assert the THERM pin.

Bit 0- ITHERM - This bit is set when the Internal Diode channel exceeds its programmed Therm Limit.

When set, this bit will assert the THERM pin.

6.18

Filter Control Register 40h

The Filter Configuration Register controls the digital filter on the External Diode 1 channel.

Table 6.22 Therm Limit Status Register

ADDR.

R/W

DEFAULT

37h

R-C

Therm

Limit

Status

THERM

ITHERM

00h

Table 6.23 Filter Configuration Register

ADDR.

R/W

DEFAULT

40h

R/W

Filter Control

FILTER[1:0]

00h

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