TVP7002IPZP datasheet(28/58 Pages) TI1

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TVP7002

SLES206C – MAY 2007 – REVISED APRIL 2013

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H-PLL Phase Select

Subaddress

04h

Default (80h)

Phase Select [4:0]

Reserved

DIV2

Phase Select [4:0]: ADC sampling clock phase select. (1 LSB = 360/32 = 11.25°). A host-based automatic phase control algorithm can be

used to control this setting to optimize graphics sampling phase.

00h = 0 degrees

10h = 180 degrees (default)

1Fh = 348.75 degrees

DIV2: DATACLK divide-by-2. H-PLL post divider. May be used with a 2x H-PLL feedback divider to improve jitter at low frequencies. When

used, only half of the Phase Select [4:0] settings are functional.

0 = DATACLK/1 (default)

1 = DATACLK/2

Clamp Start

Subaddress

05h

Default (32h)

Clamp Start [7:0]

Clamp Start [7:0]: Positions the clamp signal an integer number of clock periods after the HSYNC signal. If external clamping is selected

this value has no meaning. Clamp Start must be correctly positioned for proper operation. See Table 13 for the recommended settings.

Clamp Width

Subaddress

06h

Default (20h)

Clamp Width [7:0]

Clamp Width [7:0]: Sets the width in pixels for the fine clamp. See also register Clamp Start (subaddress 05h).

Table 13. Recommended Fine Clamp Settings

VIDEO STANDARD

CLAMP START

CLAMP WIDTH

HDTV (tri-level)

50 (32h)

32 (20h)

SDTV (bi-level)

6 (06h)

16 (10h)

PC graphics

6 (06h)

16 (10h)

HSYNC Output Width

Subaddress

07h

Default (20h)

HSOUT Width [7:0]

HSOUT Width [7:0]: Sets the width in pixels for HSYNC output.

Blue Fine Gain

Subaddress

08h

Default (00h)

Blue Fine Gain [7:0]

Blue Fine Gain [7:0]: 8-bit fine digital gain (contrast) for Blue channel (applied after the ADC). Offset binary value.

Blue Fine Gain = 1 + Blue Fine Gain [7:0]/256

Blue Fine Gain [7:0]

Blue Fine Gain

00h

1.0 (default)

80h

1.5

FFh

2.0

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