MRF24XA-ISLASHMQ datasheet(35/258 Pages) MICROCHIP

35 / 258 page

 2015 Microchip Technology Inc.

Preliminary

DS70005023C-page 35

MRF24XA

TXCON (TRANSMIT CONTROL REGISTER)

ADDRESS: 0x12

R/W/HC-0

R/W-0

R/W/HC-0

R/HS/HC-1

R/W-1

R/W-011

TXST

DTSM

TXENC

TXBUFEMPTY

CSMAEN

DR<2:0>

bit 7

bit 0

Legend: R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

r = Reserved

HC = Hardware Clear

HS = Hardware Set

bit 7

TXST: Transmit Start bit

1 = Starts the transmission of the next TX packet(1, 2)

0 = Termination of current TX operation, which may result in the transmission of an incomplete packet

Hardware Clear:

• Once the packet is successfully transmitted (including all attempted retransmissions, if any), the

hardware clears this bit and sets the TXIF and IDLEIF.

• If the packet transmission fails due to a CSMA failure, this bit is cleared, and TXCSMAIF is set.

• If Acknowledge is requested (AckReq bit field in the transmitted frame is set) and not received

after the configured number of retransmissions (TXRETMCNT), then TXST bit is cleared, and

TXACKIF is set.

• In TX-Streaming mode (TRXMODE), TXST is set even when it is already set, resulting in a

posted start. When the current TX operation completes, the posted start immediately starts

afterward. Clearing of the TXST bit clears both the current and the posted (pending) TX starts.

TXOVFIF is set when TXST = 1, a posted start is present and a Host Controller write to the

packet buffer occurs. Outside of TX-Streaming mode, writes to TXST when TXST is already set

is ignored.

Clearing this bit aborts the current operation in these cases:

• When transmitting a packet in Packet mode or in TX-Streaming mode

• When waiting for an ACK packet after a transmission

• During the CSMA CA algorithm

• When transmitting a repeated frame

This field is read at any time to determine if TX operation is in progress.

bit 6

DTSM: Do Not Touch Security Materials bit(2)

1 = Device does not change the security material configured by the host MCU

0 = Device tries to configure the security material related registers

MCU must fill the following registers: SECNONCE, SECHDRINDX, SECPAYINDX and SECEND-

INDX.

bit 5

TXENC: TX Encryption

Setting this bit starts the TX security processing (authentication or encryption, or both) of the packet

in the buffer it was last written. TXENC is cleared and TXENCIF is set when the processing is com-

plete. TXENC must be issued when NWK layer security needs to be processed. 802.15.4-2003/2006

MAC layer security operation is automatically performed when TXST bit is set. Note that this field

must not be modified while TXST is set.

Note 1: Transmission may include automatic security processing, CRC appending, CSMA-CA channel access,

Acknowledge reception and retransmissions depending on the register Configuration and the Frame Con-

trol field of the frame to be transmitted.

2: DTSM has no relevance in reception as the host can always reconfigure the security material before set-

ting RXDEC.

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