CS9211 datasheet(23/62 Pages) NSC

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Functional Description (Continued)

3.2.3.2

Output Timing Signals

There are two separate pass-through bits to select internal

or external generation of the output timing signals. The

PASS_THRU bit, Offset 404h[30] is global and affects

whether Offset 400h[7:0], Offset 404h[29], and Offset

404h[27:24] control bits will apply or not. The second pass-

through is the HSYNC_SRC bit, Offset 400h[27], and it

determines if the incoming FP_HSYNC pulse will be

passed through unmodified or not. See Table 3-8 on page

24 for descriptions on these bits.

HSYNC

Two groups of bits (Offset 400h[7:5] and Offset 400h[4:0])

control the positions of the leading and trailing edges of the

output HSYNC pulse, also called LP (Latch Pulse), LINE,

or CL1 for some panels. These two groups are effective

only if HSYNC_SRC, Offset 400h[27], is set to 1.

Regardless of the input or output polarity, the two groups of

bits move the leading and trailing edges of the output

HSYNC pulse with respect to the leading edge of the input

HSYNC pulse, as shown in Figure 3-8. Note the difference

between the terms “leading edge” and “rising edge”, and

“trailing edge” and “falling edge”.

Offset 400h[7:5] controls the position of the leading edge of

the output HSYNC pulse with respect to the leading edge

of the input HYSNC pulse. The leading edge of the output

pulse may be delayed with respect to the leading edge of

the input HYSNC pulse in increments of one DOTCLK.

Table 3-6 details the amount of delay in DOTCLK incre-

ments for each setting of Offset 400h[7:5]; note that there

is a skip in the otherwise logical order of increasing delays

from 000 to 001.

Offset 400h[4:0] controls the position of the trailing edge of

the output HSYNC pulse with respect to the leading edge

of the input HYSNC pulse. The trailing edge of the output

pulse may be delayed with respect to the leading edge of

the input HYSNC pulse in increments of one DOTCLK.

Table 3-6 details the amount of delay in DOTCLK incre-

ments for each setting of Offset 400h[4:0]; note that a set-

ting of 00000 will result in no output pulse. Note also that

with this scheme it is possible to erroneously program an

output pulse whose trailing edge occurs before the leading

edge! In such a case there will be no output pulse.

The polarity of the HSYNC output pulse may be controlled

by Offset 404h[22], only if Offset 404h[26] = 1.

Figure 3-8. Control of HSYNC Output

HSYNC

Input

HSYNC

Output

(Pin 97)

(Pin 31)

Leading Edge

controlled by

Offset 400h[7:5]

Trailing Edge

controlled by

Offset 400h[4:0]

Position

Table 3-6. HSYNC Edge Position Control

HSYNC Leading Edge

HSYNC Trailing Edge

Offset

400h[7:5]

No. of

DOTCLK

Delays

Offset

400h[4:0]

No. of

DOTCLK

Delays

Offset

400h[4:0]

No. of

DOTCLK

Delays

Offset

400h[4:0]

No. of

DOTCLK

Delays

Offset

400[4:0]

No. of

DOTCLK

Delays

000

00000

No Pulse

01000

10000

11000

001

00001

01001

10001

11001

010

00010

01010

10010

11010

011

00011

01011

10011

11011

100

00100

01100

10100

11100

101

00101

01101

10101

11101

110

00110

01110

10110

11110

111

00111

01111

10111

11111

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