CS9211 datasheet(36/62 Pages) NSC

36 / 62 page

www.national.com

Revision 2.1

Functional Description (Continued)

3.2.12 Power Sequence Control

The CS9211 contains a power-sequence controller that

manages the application of the power and control voltages

to the panel in a specified order compatible with most panel

types. Table 3-18 shows the register control bits for power

sequencing and Figure 3-13 on page 37 identifies the

power sequence and the various delays.

Four panel power control functions are managed by the

CS9211’s power sequence controller. With reference to

Figure 3-13, these are:

FP_VDDEN, Flat Panel VDD Enable: This signal is

designed to enable the basic panel power VDD. It is

intended that this signal be connected to a power FET

or similar switching device (either internal to the panel

or not) that supplies VDD to the panel, when enabled

by this signal. It should not be used as the source of

VDD to the panel.

Data and Control Signal: Activity on the data and con-

trol lines to the panel is managed as part of the power

control sequence.

FP_VCONEN, Flat Panel Voltage Contrast Enable:

This signal is designed to enable the contrast voltage

to the panel. It is intended that this signal be con-

nected to a power FET or similar switching device

(either internal to the panel or not) that supplies the

contrast voltage to the panel, when enabled by this

signal. It should not be used as the source of contrast

voltage to the panel.

DISPOFF#, Disable Backlight Off: This signal is

intended to control the backlight of the panel. It is an

active-low signal; when asserted (low), it turns the

backlight off.

3.2.12.1 External Power Sequencing

Offset 408h[27] selects whether power sequencing will be

controlled externally or internally. If external sequencing is

selected, then Offset 408h[24:18] do not have any effect.

When external power sequencing is selected, output

FP_VDDEN

directly

follows

input

ENA_VDDIN,

and

FP_VCONEN follows input ENA_LCDIN. The DISPOFF#

signal may be directly controlled by writing to Offset

408h[25].

3.2.12.2 Internal Power Sequencing

Offset 408h[27] selects whether power sequencing will be

controlled externally or internally. If internal sequencing is

selected, then the four functions listed above are controlled

automatically by the CS9211.

When operating using internal power sequencing, a power-

up or down sequence is initiated by writing to the Panel

Power Control bit at Offset 408h[24]. When the Panel

Power Control bit is low and written high, a panel power-up

sequence will occur, following the order given in Figure 3-

13 and the timings as selected by Offset 408h[23:21]. If the

Panel Power Control bit is high and written low, a panel

power-down sequence will occur, following the order given

in Figure 3-13 and with the timings as selected by Offset

408h[20:18].

The Panel Power Control bit may be read at any time in

order to determine the assumed state of the panel. If the bit

is high, it is assumed that a low-to-high transition has previ-

ously occurred and the panel is on. If the bit is low, it is

assumed that either the bit has never been set high or a

high-to-low transition of the bit has previously occurred; in

either case the panel is off.

The length of each of the phase delays during the power-

up and down sequences may be set to one of two values

(32 msor 128 ms) byPhase ControlbitsatOffset

408h[23:18]. The delay controlled by each of these bits is

diagrammed in Figure 3-13.

Table 3-18. Power Sequence Control Bits

Bit

Name

Description

Offset 408h-40Bh

Power Management Register (R/W)

Reset Value = 00000000h

PWR_SEQ_SEL

Power Sequence Select: Selects whether to use internal or external power sequence. The power

sequence controls the order in which FP_VDDEN, FP_VCONEN, the data and control signals, and

DISPOFF# become active during power-up, and inactive during power-down.

0 = Use internal power sequencing (phase timing is controlled by bits [24:18].

1 = Use external power sequencing (phase timing is controlled by signals generated from CS550A).

DISPOFF_CNTL

Display Off Control Source: Selects how DISPOFF# is controlled. Independent control may be

used to disable the backlight to save power, even if the panel is otherwise on.

0 = DISPOFF# is controlled by with the power-up/down sequence, internal or external mode.

1 = DISPOFF# immediately turns the backlight off.

PWR_CNTL

Panel Power Control: Initiates the internal power-up or power-down sequence. When the bit is set

from high-to-low, the internal power-down sequence is initiated with the timings as selected by Offset

408h[20:18]. When the bit is set from low-to-high, the internal power-up sequence is initiated with the

timings as selected by Offset 408h[23:21]. This bit may be read to determine the power status (i.e.,

on or off) of the panel. This bit functions as described only if the internal power sequence has been

selected by bit [27]. 0 = Powered down; 1 = Powered up.

CS9211 Datasheet(PDF) 36 Page - National Semiconductor (TI)

CS9211 Datasheet(HTML) 36 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL