CS9211 datasheet(55/62 Pages) NSC

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Electrical Specifications (Continued)

5.5.4

Memory Interface Timing

Figure 5-5. EDO DRAM Interface Signals

Table 5-10. EDO DRAM Interface Timing

Symbol

Parameter

Min (Note 1)

Max ((Note 1))

Unit

Comments (Note 2)

tOWS

OE# and WE# setup to falling RAS#

3*tD–5

tOWH

OE# and WE# hold from rising RAS#

3*tD–2

tRP

RAS# precharge time

3*tD–2

tRCD

Falling RAS# to falling CASH#, CASL#

tD–1

tCAS

CASH# and CASL# low pulse width

tD/2–6

tCP

CASH# and CASL# precharge time

tD/2–6

tASR

MA[10:0] setup to falling RAS#

3*tD–2

tRAH

MA[10:0] hold from falling RAS#

tD–1.5

tASC

MA[10:0] setup to falling CASH#, CASL#

tD/2–6

tCAH

MA[10:0] hold from falling CASH#, CASL#

tD/2–6

tDS

MD[15:0] write data setup to falling CASH#, CASL#

tD/2–10

tDH

MD[15:0] write data hold from falling CASH#, CASL#

tD/2–2

tDV

MD[15:0] read data valid from falling CASH#, CASL#

2*tD–10

2X Refresh Mode (min tD = 25 ns). tD = DOT clock (DOTCLK) period.

All AC tests, unless otherwise specified, are at: VDD = 3.14 to 3.46 (3.3V nominal), TC = 0°C to 85°C, and CL = 50 pF.

tASC

tCAH

RAS#

CASH#, CASL#

MA[10:0]

MD[15:0]

OE#

WE#

tRP

tOWS

tOWH

tRCD

tCAS

tCP

tASR

tRAH

tDS

tDH

MD[15:0]

tDV

(write)

(read)

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