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BD9102FVM BD9104FVM

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© 2012 ROHM Co., Ltd. All rights reserved.

TSZ22111･14･001

TSZ02201-0J3J0AJ00340-1-2

24.Oct.2013 Rev.003

Since the Current Mode Control is designed to limit an inductor current, a pole (phase lag) appears in the low frequency

area due to a RC filter consisting of an output capacitor and a load resistance, while a zero (phase lead) appears in the

high frequency area due to the output capacitor and its ESR. Therefore, the phases are easily compensated by

adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier.

Stable feedback loop may be achieved by canceling the pole fp (Min) produced by the output capacitor and the load

resistance with RC zero correction by the error amplifier.

Figure 42. Open Loop Gain Characteristics

Figure 43. Error Amp Phase Compensation Characteristics

Pole at power amplifier

When the output current decreases, the load resistance Ro

increases and the pole frequency decreases.

Zero at power amplifier

Increasing capacitance of the output capacitor lowers the pole

frequency while the zero frequency does not change. (This

is because when the capacitance is doubled, the capacitor

ESR is reduced to half.)

GND,PGND

SW

VCC,PVCC

EN

VOUT

ITH

L

ESR

Figure 44. Typical Application

Gain

[dB]

Phase

[deg]

A

0

0

-90

fp(Min)

fp(Max)

A

0

0

-90

Gain

[dB]

Phase

[deg]





 

load

lighter

with

Hz

Co

R

fp

OMax

Min











2

1





 

load

heavier

with

Hz

Co

R

fp

OMin

Max











2

1

O

O

C

R

fp









2

1





O

ESR

Z

C

ESR

f









2

1

ITH

ITH

Amp

Z

C

R

f









2

1

.)

(









O

Max

O

ITH

ITH

Min

P

Amp

Z

C

R

C

R

f

f



















2

1

2

1

.