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MCP39F511-E/MQ Datasheet(PDF) 6 Page - Microchip Technology |
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MCP39F511-E/MQ Datasheet(HTML) 6 Page - Microchip Technology |
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6 / 62 page ![]() MCP39F511 DS20005393B-page 6 2015 Microchip Technology Inc. DC Common Mode Rejection Ratio DC CMRR — -105 — dB VCM varies from -1V to +1V 10-Bit SAR ADC Performance for Temperature Measurement Resolution NR —10 — bits Absolute Input Voltage VIN DGND -0.3 — DVDD +0.3 V Recommended Impedance of Analog Voltage Source RIN —— 2.5 k Integral Nonlinearity INL —±1 ±2 LSb Differential Nonlinearity DNL —±1 ±1.5 LSb Gain Error GERR —±1 ±3 LSb Offset Error EOFF —±1 ±2 LSb Temperature Measurement Rate — fLINE/2N —sps Note 7 Clock and Timings UART Baud Rate UDB 1.2 (8) — 115.2 kbps See Section 3.2 for protocol details Master Clock and Crystal Frequency fMCLK -2% 4 +2% MHz Capacitive Loading on OSCO pin COSC2 — — 15 pF When an external clock is used to drive the device Internal Oscillator Tolerance fINT_OSC —2 — % -40 to +85°C only (Note 7) Internal Voltage Reference Internal Voltage Reference Tolerance VREF -2% 1.2 +2% V Temperature Coefficient TCVREF — 10 — ppm/°C TA = -40°C to +85°C, VREFEXT = 0 Output Impedance ZOUTVREF —2 — k Current, VREF AIDDVREF —40 — µA Voltage Reference Input Input Capacitance — — 10 pF Absolute Voltage on VREF+ Pin VREF+ AGND + 1.1V — AGND +1.3V V TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = +2.7 to +3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. 2: Specification by design and characterization; not production tested. 3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL =80 ms for 50 Hz line. 4: Applies to Voltage Sag and Voltage Surge events only. 5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. 6: VIN =1VPP = 353 mVRMS @ 50/60 Hz. 7: Variation applies to internal clock and UART only. All calculated output quantities are temperature compensated to the performance listed in the respective specification. 8: Lower baud rates selectable only on system versions 0xFA14 and later. |
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