MT9072AB datasheet(203/275 Pages) ZARLINK

203 / 275 page

MT9072

Data Sheet

203

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

not used.

Sa5VI

Sa5 Value Bit Interrupt. This bit is one when the corresponding latched status bit (Sa5VL,

address Y46). This bit is cleared when either this register, or the latched status register is read.

Sa6V3I

Sa6V2I

Sa6V1I

Sa6V0I

Sa6 Value Bits 3-0 Interrupt. This bit is one when the corresponding latched status bit

(Sa6V*L, register address Y26) is set, and the corresponding mask bit is unmasked (Sa6V*M,

is read.

9Sa6N8I

Eight Consecutive Sa6 Nibbles Interrupt. This bit is one when the corresponding latched

status bit (Sa6N8L, register address Y26) is set, and the corresponding mask bit is unmasked

(Sa6N8M, register address Y46). This bit is cleared when either this register, or the latched

status register is read.

Sa6NI

Sa6 Nibble Change Interrupt. This bit is one when the corresponding latched status bit

(Sa6NL, register address Y26) is set, and the corresponding mask bit is unmasked (Sa6NM,

is read.

7SaNI

Sa Nibble Change Interrupt. This bit is one when the corresponding latched status bit (SaNL,

address Y46). This bit is cleared when either this register, or the latched status register is read.

Sa5TI

Sa5 Bit Change Interrupt. This bit is one when the corresponding latched status bit (Sa5TL,

address Y46). This bit is cleared when either this register, or the latched status register is read.

5SaTI

Sa Bit Change Interrupt. This bit is one when the corresponding latched status bit (SaTL,

address Y46). This bit is cleared when either this register, or the latched status register is read.

4CASRI

Receive Channel Associated Signaling (CAS) Interrupt. is bit is one when the

corresponding latched status bit (CASRL, register address Y24) is set, and the corresponding

mask bit is unmasked (CASRM, register address Y44). This bit is cleared when either this

3CALNI

CRC-4 Alignment 2 ms Timer Interrupt. This bit is one when the corresponding latched

status bit (CALNL, register address Y26) is set, and the corresponding mask bit is unmasked

(CALNM, register address Y46). This bit is cleared when either this register, or the latched

status register is read.

Table 180 - CAS, National, CRC-4 Local and Timer Interrupt Status Register (Address Y36) (E1)

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