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MT9072AB Datasheet(PDF) 264 Page - Zarlink Semiconductor Inc |
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MT9072AB Datasheet(HTML) 264 Page - Zarlink Semiconductor Inc |
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264 / 275 page  MT9072 Data Sheet 264 Zarlink Semiconductor Inc. Figure 65 - Transmit Data Link Pin Timing AC Electrical Characteristics - Transmit Data Link Pin Timing Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 Clock Delay tCD 55 ns 150 pF load on TxDLC 2 Enable Delay tED 55 ns 150 pF load on TxDLC 3Data Setup tDS 100 ns 4Data Hold tDH 50 ns MT9072 Inputs Data tDH tDS ST-BUS Bit Cells 2Mb/s CKi (ST-BUS C4i) 2Mb/s VT TxDL (Input) VT Note 1 - TxDLC output applies for every second frame (FPi) pulse (250 us) only Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y08) Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y08) tED tED TxDLC - Note 3 (Output) VT VT tCD tCD TxDLC - Note 2 (Output) ST-BUS Bit Cells 8Mb/s CKi (ST-BUS C16i) 8Mb/s VT |
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