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MT9072AB Datasheet(PDF) 267 Page - Zarlink Semiconductor Inc |
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MT9072AB Datasheet(HTML) 267 Page - Zarlink Semiconductor Inc |
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267 / 275 page  MT9072 Data Sheet 267 Zarlink Semiconductor Inc. Figure 68 - Receive Data Link Timing AC Electrical Characteristics - Receive Data Link Timing Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 Clock Delay tCD 55 ns 150 pF load on RxDLC 2 Enable Delay tED 55 ns 150 pF load on RxDLC 3 Data Delay Read tDDR 125 ns 150 pF load on RxDL MT9072 Outputs Data tCD VT VT VT tDDR tCD RxDLC - Note 2 (Output) RxDL (Output) E2i RXDL Bit Cells VT tED tED RxDLC - Note 3 (Output) Note 1 - RxDLC output applies for every second frame (RxBF) pulse (250us) only Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y08) Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y08) Note 4 - The PCM 30 Timeslots are with respect to RXDL Output |
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