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MT9072AB Datasheet(PDF) 266 Page - Zarlink Semiconductor Inc |
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MT9072AB Datasheet(HTML) 266 Page - Zarlink Semiconductor Inc |
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266 / 275 page  MT9072 Data Sheet 266 Zarlink Semiconductor Inc. Figure 67 - Receive Basic Frame and E4o Timing AC Electrical Characteristics - Receive Basic Frame and E4o Timing Characteristics Sym. Min. Typ. Max. Units Test Conditions 1 Basic Frame Output Delay tBD 30 115 ns 150 pF load on RxBF 2 Clock Delay tCD 55 ns 150 pF load on RxDLC 3E4o Clock High Width tE4HW 50 200 ns 150 pF load on RxDLC 3E4o Clock Low Width tE4LW 25 75 ns 150 pF load on RxDLC VT Timeslot 31 Bit 8 Timeslot 0 Bit 1 VT RxBF (Output) E2i Input RXDL PCM 30 Bit Cells E4o - Note 1 (RxDLC Pin) Output tCD tCD Note 1 - The E4o signal is output at the RxDLC Pin when the E4CK control bit (address Y08) is set to one. Note 2 - The PCM Timeslots are referred to RXDL Output which is delayed 4 bits from the RPOS/RNEG input. Note3- The E4o Clock(RXDLC Output) is not a 50% duty cycle clock, it will be low for 25 % and high for 75% of the 4.096 MHz clock VT tE4HW tE4LW tBD t BD |
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