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PRELIMINARY

AT91SAM7A1 Summary

6048AS–ATARM–07/04

fast interrupt request input, the FIQ. The nIRQ line can be asserted by the interrupts

generated by the on-chip peripherals and the external interrupt request line, IRQ0. An 8-

level priority encoder allows the customer to define the priority between the different

nIRQ interrupt sources. Internal sources are programmed to be level sensitive or edge

triggered. External sources can be programmed to be positive or negative edge trig-

gered or high or low level sensitive.

Parallel I/O Controller

(PIO)

The AT91SAM7A1 has 49 configurable I/O lines. Thirty-two pins (unified PIO) on the

AT91SAM7A1 are dedicated as general purpose I/O pins (UPIO0 - UPIO31). Other I/O

lines are multiplexed with an external signal of a peripheral to optimize the use of avail-

able package pins. The unified PIO pins are controlled by a dedicated module; the

others pins are configured in each module.

Peripheral Data

Controller (PDC)

An on-chip, 11-channel Peripheral Data Controller (PDC) transfers data between the on-

chip peripherals and the on- and off-chip memories without processor intervention. One

PDC channel is connected to the receiving channel and one to the transmitting channel

of each USART and of the SPI. A single PDC channel is connected to each ADC and

each Capture.

Most importantly, the PDC removes the processor interrupt handling overhead and sig-

nificantly reduces the number of clock cycles required for a data transfer. It can transfer

up to 64 Kbytes without reprogramming the starting address. As a result, the perfor-

mance of the microcontroller is increased and the power consumption reduced.

Universal

Synchronous/

Asynchronous

Receiver/Transmitter

(USART)

The AT91SAM7A1 provides three identical, full-duplex Universal Synchronous/Asyn-

chronous Receiver/Transmitters that are connected to the Peripheral Data Controller.

The main features are:

•

Programmable Baud Rate Generator

•

Parity, framing and overrun error detection

•

Line break generation and detection

•

Automatic echo, local & remote loopback modes

•

Multi-drop mode: address detection and generation

•

Interrupt generation

•

Two Dedicated Peripheral Data Controller channels

•

5-, 6-, 7-, 8- and 9-bit character length

•

Idle flag for J1587 protocol.

•

Smart card transmission error feature

•

Support LIN 1.2 protocol with H/W layer

Serial Peripheral

Interface (SPI)

The AT91SAM7A1 features an SPI that provides communication with external devices

in master or slave mode. The SPI has four external chip selects that can be connected

to up to 15 devices. The data length is programmable from 8-bit to 16-bit.

As for the USART, a two-channel PDC is used to move data directly between memory

and the SPI without CPU intervention for maximum real-time processing throughput.