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VND7004AY Datasheet(PDF) 15 Page - STMicroelectronics |
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VND7004AY Datasheet(HTML) 15 Page - STMicroelectronics |
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15 / 47 page ![]() VND7004AY Electrical specification DocID027772 Rev 9 15/47 7 V < VCC < 18 V; -40°C < Tj < 150°C Symbol Parameter Test conditions Min. Typ. Max. Unit tDSENSE1L Current sense disable delay time from falling edge of SEn VIN = 5 V; VSEn = 5 V to 0 V; RSENSE = 1 kΩ; RL = 0.87 Ω 5 20 µs tDSENSE2H Current sense settling time from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 kΩ; RL = 0.87 Ω 170 400 µs ΔtDSENSE2H Current sense settling time from rising edge of IOUT (dynamic response to a step change of IOUT) VIN = 5 V; VSEn = 5 V; RSENSE = 1 kΩ; ISENSE = 90 % of ISENSEMAX; RL = 0.87 Ω 200 µs tDSENSE2L Current sense turn-off delay time from falling edge of INPUT VIN = 5 V to 0 V; VSEn = 5 V; RSENSE = 1 kΩ; RL = 0.87 Ω 50 250 µs MultiSense timings (chip temperature sense mode - see Figure 6: "Multisense timings (chip temperature and VCC sense mode)")(4) tDSENSE3H VSENSE_TC settling time from rising edge of SEn VSEn = 0 V to 5 V; VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 kΩ 60 µs tDSENSE3L VSENSE_TC disable delay time from falling edge of SEn VSEn = 5 V to 0 V; VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 kΩ 20 µs MultiSense timings (VCC voltage sense mode - see Figure 6: "Multisense timings (chip temperature and VCC sense mode)")(4) tDSENSE4H VSENSE_VCC settling time from rising edge of SEn VSEn = 0 V to 5 V; VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 kΩ 60 µs tDSENSE4L VSENSE_VCC disable delay time from falling edge of SEn VSEn = 5 V to 0 V; VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 kΩ 20 µs MultiSense timings (Multiplexer transition times)(4) tD_XtoY MultiSense transition delay from ChX to ChY VIN0 = 5 V; VIN1 = 5 V; VSEn = 5 V; VSEL1 = 0 V; VSEL0 = 0 V to 5 V; IOUT0 = 0 A; IOUT1 = 15 A; RSENSE = 1 kΩ 20 µs tD_CStoTC MultiSense transition delay from current sense to TC sense VIN0 = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V to 5 V; IOUT0 = 1.5 A; RSENSE = 1 kΩ 60 µs |
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