27

Note:

* Post-radiation performance guaranteed at 25

1. If max exceeded, additional wait state occurs.

3. Assuming back-to-back bus cycles.

4. 8-bit only

5. Tested only at initial qualification, and after any design or process changes which may affect this characteristic.

6. These specs are verified using functional vectors (strobed) only.

7. Low speed tests performed at 5MHz. 1MHz operation is guaranteed by design.

5

ALE falling edge to WR falling edge

ns

CLKOUT low to WR falling edge

-5

+10

ns

2

Data stable to WR rising edge

T

T

ns

5

CLKOUT high to WR rising edge

-10

+15

ns

2,5

WR low period

ns

t

WHQX

5

Data hold after WR rising edge

ns

t

WHLH

3,5

WR rising edge to ALE rising edge

ns

5

BHE, INST after WR rising edge

ns

4,5

AD8-15 HOLD after WR rising

T

ns

5

BHE, INST after RD rising edge

T

T

ns

4,5

AD8-15 HOLD after RD rising

ns

5

Address valid to EDACEN valid

ns

t

LHENX

5

EDACEN hold after ALE high

0

ns

t

AVEV

2,5

Address valid to EDAC input valid

ns

5

EDAC hold after RD inactive

0

T

ns

2,5

EDAC output stable to WR rising

T

T

ns

5

EDAC output hold after WR rising

T

T

ns