AK4456 datasheet(21/84 Pages) AKM

21 / 84 page

[AK4456]

015006886-E-00

2015/06

- 21 -

(Ta=-40  105C; AVDD=3.0  5.5V, TVDD=1.62  1.98V / 3.0  3.6V)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Control Interface Timing (3-wire Serial mode):

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN “H” Time

CSN “” to CCLK “”

CCLK “” to CSN “”

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

200

150

nsec

Control Interface Timing (I

2C Bus mode):

SCL Clock Frequency

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first clock pulse)

Clock Low Time

Clock High Time

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling

(Note 30)

SDA Setup Time from SCL Rising

Rise Time of Both SDA and SCL Lines

Fall Time of Both SDA and SCL Lines

Setup Time for Stop Condition

Pulse Width of Spike Noise Suppressed by Input Filter

Capacitive load on bus

fSCL

tBUF

tHD:STA

tLOW

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tSU:STO

tSP

1.3

0.6

1.3

0.6

0.1

0.6

400

1.0

0.3

400

kHz

sec

nsec

Power-down & Reset Timing

(Note 31)

PDN Accept Pulse Width

PDN Reject Pulse Width

tAPD

tRPD

150

nsec

Note 30. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Note 31.The AK4456 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held “L”

for more than 150ns for a certain reset. The AK4456 is not reset by the “L” pulse less than 30ns.

Note 32. I

2C is a trademark of NXP B.V.

AK4456 Datasheet(PDF) 21 Page - Asahi Kasei Microsystems

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