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STGIPN3H60-H Datasheet(PDF) 17 Page - STMicroelectronics |
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STGIPN3H60-H Datasheet(HTML) 17 Page - STMicroelectronics |
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17 / 23 page ![]() STGIPN3H60-H Application circuit example DocID024132 Rev 4 17/23 5.1 Guidelines Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull down resistor is built- in for each input. If an external RC filter is used, for noise immunity, pay attention to the variation of the input signal level. To prevent input signal oscillation, the wiring of each input should be as short as possible. By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-coupler is possible. Each capacitor should be located as close as possible to the pins of the IPM. Low inductance shunt resistors should be used for phase leg current sensing. Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitors mounted close to the module pins will further improve performance. The SD /OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see Section 4: "Smart shutdown function" for detailed info). These guidelines are useful for application design to ensure the specifications of the device. For further details, please refer to the relevant application note AN4043. Table 15: Recommended operating conditions Symbol Parameter Test conditions Min. Typ. Max. Unit VPN Supply voltage Applied between P-Nu, Nv, Nw 300 500 V VCC Control supply voltage Applied between VCC-GND 13.5 15 18 V VBS High side bias voltage Applied between VBOOTi-OUTi for i = U, V, W 13 18 V tdead Blanking time to prevent Arm-short For each input signal 1.5 µs fPWM PWM input signal -40°C < Tc < 100 °C -40°C < Tj < 125 °C 25 kHz TC Case operation temperature 100 °C |
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