A6984 datasheet(23/47 Pages) STMICROELECTRONICS

23 / 47 page

DocID030396 Rev 1

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A6984

Device description

As a consequence, the injected triangular voltage ripple in the FB is:

Equation 15

that does not depend on the R2, R3, CDC, L and DCR.

A virtual ESR network able to guarantee a peak-to-peak signal higher than 20 mV at the FB

pin removes any duty cycle dithering at the switching node.

Output voltage accuracy and optimized resistor divider

The constant on-time control scheme implements valley output voltage regulation: the

internal comparator monitors the FB voltage cycle-by-cycle and generates a fixed TON pulse

if the sensed voltage drops below the internal voltage reference (VEAFB = 0.9 V typical).

The virtual ESR network generates a signal proportional to the inductor current that is AC

coupled to the FB pin through the CDC capacitor (refer to Section 4.3 for dimensioning rules)

and superimposed on the voltage divider contribution as shown in Figure 16.

VFB

RIPPLE VIN



RIPPLE

ESR

VRT



OUT

–

COT



----------------------------------

OUT

--------------

fsw

---------



A6984 Datasheet(PDF) 23 Page - STMicroelectronics